000			07313nam a22001815i 4500
020			_a9788131222744 (pb)
040			_cCUS
082			_a005.275 _bPAT/C
100	1		_aPatterson, David. _922388
245	1	0	_aComputer organization and design: the hardware software interface / _cDavid Patterson and John Hennessy.
250			_a4th ed.
260			_aHaryana : _bElsevier , _c2010.
300			_axxv, 689 p. _bill. ;
504			_aincludes index
505			_a1.1 Introduction 1.2 Below Your Program 1.3 Under the Covers 1.4 Performance 1.5 The Power Wall 1.6 The Sea Change: The Switch from Uni processors to Multiprocessors 1.7 Real Stuff: Manufacturing and Benchmarking the AMD Opteron X4 1.8 Fallacies and Pitfalls 1.9 Concluding Remarks 1.10 Historical Perspective and Further Reading 1.11 Exercises 2.1 Introduction 2.2 Operations of the Computer Hardware 2.3 Operands of the Computer Hardware 2.4 Signed and Unsigned Numbers 2.5 Representing Instructions in the Computer 2.6 Logical Operations 2.7 Instructions for Making Decisions 2.8 Supporting Procedures in Computer Hardware 2.9 Communicating with People 2.10 ARM Addressing for 32-Bit Immediates and More Complex Addressing Modes 2.11 Parallelism and Instructions: Synchronization 2.12 Translating and Starting a Program 2.13 AC Sort Example to Put It AH Together 2.14 Arrays versus Pointers 2.15 Advanced Material: Compiling C and Interpreting Java 2.16 Real Stufif: MIPS Instructions 2.17 Real Stuff; x86 Instructions 2.18 Fallacies and Pitfalls 2.19 Concluding Remarks 2.20 Historical Perspective and Further Reading 2.21 Exercises 3.1 Introduction 3.2 Addition and Subtraction 3.3 Multiplication 3.4 Division 3.5 Floating Point 3.6 Parallelism and Computer Arithmetic: Associativity 3.7 Real Stuff: Floating Point in the x86 3.8 Fallacies and Pitfalls 3.9 Concluding Remarks 3.10 Historical Perspective and Fiuther Reading 3.11 Exercises 4.1 Introduction 4.2 Logic Design Conventions 4.3 Building a Datapath 4.4 A Simple Implementation Scheme 4.5 An Overview of Pipelining 4.6 Pipelined Datapath and Control 4.7 Data Hazards: Forwarding versus Stalling 4.8 Control Hazards 4.9 Exceptions 4.10 Parallelism and Advanced Instruction-Level Parallelism 4.11 Real Stuff; the AMD Opteron X4 (Barcelona) Pipeline 4.12 Advanced Topic: an Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations 4.13 Fallacies and Pitfalls 4.14 Concluding Remarks 4.15 Historical Perspective and Further Reading 4.16 Exercises Large and Fast: Exploiting Memory Hierarchy 5.1 Introduction 5.2 The Basics of Caches 5.3 Measuring and Improving Cache Performance 5.4 Virtual Memory 5.5 A Common Framework for Memory Hierarchies 5.6 Virtual Machines 5.7 Using a Finite-State Machine to Control a Simple Cache 5.8 Parallelism and Memory Hierarchies: Cache Coherence 5.9 Advanced Material: Implementing Cache Controllers 5.10 Real Stuffi the AMD Opteron X4 (Barcelona) and Intel Nehalem Memory Hierarchies 5.11 Fallacies and Pithdls 5.12 Concluding Remarks 5.13 Historical Perspective and Further Reading 5.14 Exercises Storage and Other I/O Topics 6.1 Introduction 6.2 Dependability, Reliability, and Availability 6.3 Disk Storage 6.4 Flash Storage 6.5 Connecting Processors, Memory, and I/O Devices 6.6 Interfacing I/O Devices to the Processor, Memory, and Operating System 6.7 I/O Performance Measures: Examples from Disk and File Systems 6.8 Designing an I/O System 6.9 Parallelism and 1/0: Redundant Arrays of lne3q)ensive Disks 6.10 Real Stuffi Sun Fire x4150 Server 6.11 Advanced Topics: Networks 6.12 Fallacies and Pitfalls 6.13 Concluding Remarks 6.14 Historical Perspective and Further Reading 6.15 Exercises Muitlcores, Multiprocessors, and Clusters 7.1 Introduction 7.2 The Difficulty of Creating Parallel Processing Programs 7.3 Shared Memory Multiprocessors 7.4 Clusters and Other Message-Passing Multiprocessors 7.5 Hardware Multithreading 7.6 SISD, MIMD, SIMD, SPMD, and Vector 7.7 Introduction to Graphics Processing Units 7.8 Introduction to Multiprocessor Network Topologies 7.9 Multiprocessor Benchmarks 7.10 Roofline; A Simple Performance Model 7.11 Real Stuff: Benchmarking Four Multicores Using the Roofline Model 7.12 Fallacies and Pitfalls 7.13 Concluding Remarks 7.14 Historical Perspective and Further Reading 7.15 Exercises Graphics and Computing GPUs A.1 Introduction A.2 GPU System Architectures A.3 Scalable Parallelism - Programming GPUs A.4 Multithreaded Multiprocessor Architecture A.5 Parallel Memory System G.6 Floating Point A.6 Floating Point Arithmetic A.7 Real Stuff; The NVIDIA GeForce 8800 A.8 Real Stuff; Mapping Applications to GPUs A.9 Fallacies and Pitfalls A. 10 Concluding Remarks A. 11 Historical Perspective and Further Reading ARM and Thumb Assembier instructions Bl.l Using This Appendix BI.2 Syntax B1.3 Alphabetical List of ARM and Thumb Instructions B1.4 ARM Assembler Quick Reference B1.5 GNU Assembler Quick Reference ARM and Thumb Instruction Encodings B2.1 ARM Instruction Set Encodings B2.2 Thumb Instruction Set Encodings B2.3 Program Status Registers Instruction Cycie Timings B3.1 Using the Instruction Set Cycle Timing Tables B3.2 ARM7TDMI Instruction Cycle Timings B3.3 ARM9TDMI Instruction Cycle Timings B3.4 StrongARMlInstruction Cycle Timings B3.5 ARM9E Instruction Cycle Timings B3.6 ARMlOE Instruction Cycle Timings B3.7 Intel XScale Instruction Cycle Timings B3.8 ARM 11 Cycle Timings The Basics of Logic Design C.l Introduction C.2 Gates, Truth Tables, and Logic Equations C.3 Combinational Logic C.4 Using a Hardware Description Language C.5 Constructing a Basic Arithmetic Logic Unit C.6 Faster Addition: Carry Lookahead C.7 Clocks C.8 Memory Elements: Flip-Flops, Latches, and Registers C.9 Memory Elements: SRAMs and DRAMs C.IO Finite-State Machines C.ll Timing Methodologies C.l2 Field Programmable Devices C.l3 Concluding Remarks C.14 Exercises Mapping Controi to Hardware D.l Introduction D.2 Implementing Combinational Control Units D.3 Implementing Finite-State Machine Control D.4 Implementing the Next-State Function with a Sequencer D.5 Translating a Microprogram to Hardware D.6 Concluding Remarks D.7 Exercises Section 2.15 Compiling C and Interpreting Java Section 4.12 An Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations Section 5.9 Implementing Cache Controllers Section 6.11 Networks HISTORICAL PERSPECTIVES & FURTHER READING Chapter 1 Computer Abstractions and Technology: Section Chapter 2 Instructions: Language of the Computer: Section Chapter 3 Arithmetic for Computers: Section Chapter 4 The Processor: Section Chapter 5 Large and Fast: Exploiting Memory Hierarchy: Section Chapter 6 Storage and Other I/O Topics: Section Chapter 7 Multicores, Multiprocessors, and Clusters: Section Appendix A Graphics and Computing CPUs: Section A. TUTORIALS VHDL Verilog SOFT W A R E ary Xilinx FPGA Design, Simulation and Synthesis Software QEMU http://www.nongnu.org/qemu/about.htmler Reading
650			_aComputer Programming _9587
942			_cWB16
999			_c2749 _d2749