000			05093cam a22002895i 4500
020			_a9780387765303
020			_a9781441945617 (print)
040			_cCUS
082	0	4	_a005.14 _bSPE/S
100	1		_aSpear, Chris. _920854
245	1	0	_aSystem Verilog for Verification: a Guide to Learning the Testbench Language Features / _c Chris Spear.
250			_a2nd ed.
260			_aNew York : _bSpringer , _c2008.
300			_axxvi, 429 p.
505			_a1. VERIFICATION GUIDELINES 1.1 The Verification Process 1.2 The Verification Methodology Manual 1.3 Basic Testbench Functionality 1.4 Directed Testing 1.5 Methodology Basics 1.6 Constrained-Random Stimulus 1.7 What Should You Randomize? 1.8 Functional Coverage 1.9 Testbench Components 1.10 Layered Testbench 1.11 Building a Layered Testbench 1.12 Simulation Environment Phases 1.13 Maximum Code Reuse 1.14 Testbench Performance 1.15 Conclusion 2. DATA TYPES 2.1 Built-in Data Types 2.2 Fixed-Size Arrays 2.3 Dynamic Arrays 2.4 Queues 2.5 Associative Arrays 2.6 Linked Lists 2.7 Array Methods 2.8 Choosing a Storage Type 2.9 Creating New Types with typedef 2.10 Creating User-Defined Structures 2.11 Type conversion 2.12 Enumerated Types 2.13 Constants 2.14 Strings 2.15 Expression Width 2.16 Conclusion 3. PROCEDURAL STATEMENTS AND ROUTINES 3.1 Procedural Statements 3.2 Tasks, Functions, and Void Functions 3.3 Task and Function Overview 3.4 Routine Arguments 3.5 Returning from a Routine 3.6 Local Data Storage 3.7 Time Values 3.8 Conclusion 4. CONNECTING THE TESTBENCH AND DESIGN 4.1 Separating the Testbench and Design 4.2 The Interface Construct 4.3 Stimulus Timing 4.4 Interface Driving and Sampling 4.5 Connecting It All Together 4.6 Top-Level Scope 4.7 Program - Module Interactions 4.8 SystemVerilog Assertions 4.9 The Four-Port ATM Router 4.10 The ref Port Direction 4.11 The End of Simulation 4.12 Directed Test for the LC3 Fetch Block 4.13 Conclusion 5. BASIC OOP 5.1 Introduction 5.2 Think of Nouns, not Verbs 5.3 Y our F irst Class 5.4 Where to Define a Class 5.5 OOP Terminology 5.6 Creating New Objects 5.7 Object Deallocation 5.8 Using Objects 5.9 Static Variables vs. Global Variables 5.10 Class Methods 5.11 Defining Methods Outside of the Class 5.12 Scoping Rules 5.13 Using One Class Inside Another 5.14 Understanding Dynamic Objects 5.15 Copying Objects 5.16 Public vs. Local 5.17 Straying Off Course 5.18 Building a Testbench 5.19 Conclusion 6. RANDOMIZATION 6.1 Introduction 6.2 What to Randomize 6.3 Randomization in SystemVerilog 6.4 Constraint Details 6.5 Solution Probabilities 6.6 Controlling Multiple Constraint Blocks i 6.7 Valid Constraints 7. 6.8 In-line Constraints 6.9 The pre randomize and post randomize Functions 6.10 Random Number Functions 6.11 Constraints Tips and Techniques 6.12 Common Randomization Problems 6.13 Iterative and Array Constraints 6.14 Atomic Stimulus Generation vs. Scenario Generation 6.15 Random Control 6.16 Random Number Generators 6.17 Random Device Configuration 6.18 Conclusion THREADS AND INTERPROCESS COMMUNICATION 7.1 Working with Threads 7.2 Disabling Threads 7.3 Interprocess Communication 7.4 Events 7.5 Semaphores 7.6 Mailboxes 7.7 Building a Testbench with Threads and IPC 7.8 Conclusion 8. ADVANCED OOP AND TESTBENCH GUIDELINES 8.1 Introduction to Inheritance 8.2 Blueprint Pattern 8.3 Downcasting and Virtual Methods 8.4 Composition, Inheritance, and Alternatives 8.5 Copying an Object 8.6 Abstract Classes and Pure Virtual Methods 8.7 Callbacks 8.8 Parameterized Classes 8.9 Conclusion 9. FUNCTIONAL COVERAGE 9.1 Coverage Types 9.2 Functional Coverage Strategies 9.3 Simple Functional Coverage Example 9.4 Anatomy of a Cover Group 9.5 Triggering a Cover Group 9.6 Data Sampling 9.7 Cross Coverage 9.8 Generic Cover Groups 9.9 Coverage Options 9.10 Analyzing Coverage Data 9.11 Measuring Coverage Statistics During Simulation 9.12 Conclusion 10. ADVANCED INTERFACES 10.1 Virtual Interfaces with the ATM Router 10.2 Connecting to Multiple Design Configurations 10.3 Procedural Code in an Interface 10.4 Conclusion 11. A COMPLETE SYSTEMVERILOG TESTBENCH 1 1.1 Design Blocks 1 1.2 Testbench Blocks 1 1.3 Alternate Tests |]4 Conclusion 12. INTERFACING WITH C 12.1 Passing Simple Values 12.2 Connecting to a Simple C Routine 12.3 Connecting to C++ 12.4 Simple Array Sharing 12.5 Open arrays 12.6 Sharing Composite Types 12.7 Pure and Context Imported Methods 12.8 Communicating from C to SystemVerilog 12.9 Connecting Other Languages 12.10 Conclusion
650		0	_aEngineering. _915924
650		0	_aComputer hardware. _920855
650		0	_aComputer aided design. _920856
650		0	_aComputer engineering. _920857
650		0	_aSystems engineering. _920858
650	1	4	_aEngineering. _915924
650	2	4	_aCircuits and Systems. _920859
650	2	4	_aComputer-Aided Engineering (CAD, CAE) and Design. _920860
650	2	4	_aComputer Hardware. _920855
650	2	4	_aElectrical Engineering. _920861
942			_cWB16
999			_c2674 _d2674