000 04286cam a2200169 a 4500
020 _a9789381269220 (pb)
040 _cCUS
082 0 4 _a004.22
_bHEN/C
100 1 _aHennessy, John L.
_920689
245 1 0 _aComputer architecture:a quantitative approach /
_cJohn L. Hennessy, David A. Patterson
250 _a5th ed.
260 _aAmsterdam ;
_aBoston :
_bMorgan Kaufmann,
_c2007.
300 _a1 v. (various pagings) :
_c24 cm. +
505 _aChapter 1 Fundamentals of Quantitative Design and Analysis 1.1 Introduction 1.2 Classes of Computers 1.3 Defining Computer Architecture 1.4 Trends in Technology 1.5 Trends in Power and Energy in Integrated Circuits 1.6 Trends in Cost 1.7 Dependability 1.8 Measuring, Reporting, and Summarizing Performance 1.9 Quantitative Principles of Computer Design 1.10 Putting It All Together; Performance, Price, and Power 1.11 Fallacies and Pitfalls 1.12 Concluding Remarks 1.13 Historical Perspectives and References Case Studies and Exercises by Diana Franklin Chapter 2 Memory Hierarchy Design 2.1 Introduction 2.2 Ten Advanced Optimizations of Cache Performance 2.3 Memory Technology and Optimizations 2.4 Protection; Virtual Memory and Virtual Machines 2.5 Crosscutting lssues; The Design of Memory Hierarchies 2.6 Putting It All Together; Memory Hierachies in the ARM Cortex-A8 and Intel Core 17 2.7 Fallacies and Pitfalls 2.8 Concluding Remarks: Looking Ahead 2.9 Historical Perspective and References Case Studies and Exercises by Norman P. Jouppi, Naveen Muralimanohar, and Sheng Li Chapter 3 Instruction-Level Parallelism and Its Exploitation 3.1 Instruction-Level Parallelism: Concepts and Challenges 3.2 Basic Compiler Techniques for Exposing ILP 3.3 Reducing Branch Costs with Advanced Branch Prediction 3.4 Overcoming Data Hazards with Dynamic Scheduling 3.5 Dynamic Scheduling: Examples and the Algorithm 3.6 Hardware-Based Speculation 3.7 Exploiting ILP Using Multiple Issue and Static Scheduling 3.8 Exploiting ILP Using Dynamic Scheduling, Multiple Issue, and Speculation 3.9 Advanced Techniques for Instruction Delivery and Speculation 3.10 Studies of the Limitations of ILP 3.11 Cross-Cutting Issues: ILP Approaches and the Memory System 3.12 Multithreading: Exploiting Thread-Level Parallelism to Improve Uniprocessor Throughput 3.13 Putting It All Together: The Intel Core 17 and ARM Cortex-A8 3.14 Fallacies and Pitfalls 3.15 Concluding Remarks: What's Ahead? 3.16 Historical Perspective and References Case Studies and Exercises by Jason D. Bakos and Robert P. Colwell Chapter4 Data-Level Parallelism in Vector, SIMD, and GPU Architectures 4.1 Introduction 4.2 Vector Architecture 4.3 SIMD Instruction Set Extensions for Multimedia 4.4 Graphics Processing Units 4.5 Detecting and Enhancing Loop-Level Parallelism 4.6 Crosscutting Issues 4.7 Putting It All Together: Mobile versus Server CPUs and Tesia versus Core 17 4.8 Fallacies and Pitfalls 4.9 Concluding Remarks 4.10 Historical Perspective and References Case Study and Exercises by Jason D. Bakos Chapter 5 Thread-Level Parallelism 5.1 Introduction Centralized Shared-Memory Architectures Performance of Symmetric Shared-Memory Multiprocessors 5.2 5.3 5.4 Distributed Shared-Memory and Directory-Based Coherence 5.5 Synchronization: The Basics 5.6 Models of Memory Consistency: An Introduction 5.7 Crosscutting Issues 5.8 Putting It All Together: Multicore Processors and Their Performance 5.9 Fallacies and Pitfalls 5.10 Concluding Remarks 5.11 Historical Perspectives and References Case Studies and Exercises by Amr Zaky and David A. Wood Chapter 6 Warehouse-Scale Computers to Exploit Request-Level and Data-Level Parallelism 6.1 Introduction 6.2 Programming Models and Workloads for Warehouse-Scale Computers 6.3 Computer Architecture of Warehouse-Scale Computers 6.4 Physical Infrastructure and Costs of Warehouse-Scale Computers 6.5 Cloud Computing: The Return of Utility Computing 6.6 Crosscutting Issues 6.7 Putting It All Together: A Google Warehouse-Scale Computer 6.8 Fallacies and Pitfalls 6.9 Concluding Remarks 6.10 Historical Perspectives and References Case Studies and Exercises by Parthasarathy Ranganathan
650 0 _aComputer Architecture.
_98559
942 _cWB16
999 _c1797
_d1797