000			15599nam a2200169 4500
020			_a9780074622353 (pb)
040			_cCUS
082			_a004 _bMAL/D
100			_aMalvino, Albert Paul _911635
245			_aDigital computer electronics _cAlbert Paul Malvino and Jerald A. Brown
250			_a3rd ed.
260			_aNew Delhi : _bTata Mcgraw hill , _c1995.
300			_a522 p. _bill. ;
505			_aCHAPTER 6. ARITHMETIC-LOGIC UNITS PART 1 Digital Principles 1 CHAPTER 1. NUMBER SYSTEMS AND CODES 1 1-1. Decimal Odometer 1-2. Binary Odometer 1-3. Number Codes 1-4. Why Binary Numbers Are Used 1-5. Binary-to-Decimal Conversion 1-6. Microprocessors 1-7. Decimal-to-Binary Conversion 1-8. Hexadecimal Numbers 1-9. Hexadecimal-Binary Conversions 1-10. Hexadecimal-to-Decimal Conversion 1-11. Decimal-to-Hexadecimal Conversion 1-12. BCD Numbers 1-13. The ASCII Code CHAPTER 2. GATES 2-1. Inverters 2-2. or Gates 2-4. Boolean Algebra 2-3. AND Gates CHAPTER 3. MORE LOGIC GATES 3-1. NOR Gates 3-2. De Morgan's First Theorem 3-3. NAND Gates 3-4. De Morgan's Second Theorem 3-5. EXCLUSIVE-OR Gates 3-6. The Controlled Inverter 3-7. exclusive-nor Gates CHAPTER 4. TTL CIRCUITS 4-1. Digital Integrated Circuits 4-2. 7400 Devices 4-3. TTL Characteristics 4-4. TTL Overview 4-5. AND-OR-iNVERT Gates 4-6. Open-Collector Gates 4-7. Multiplexers 6-1. Binary Addition 6-2. Binary Subtraction 6-3. Half Adders 6-4. Full Adders 6-5. Binary Adders 6-6. Signed Binary NOitibers 6-7. 2's Complement 6-8. 2's-CompIement Adder-Subtracter CHAPTER 7. FLIP-FLOPS 7-1. Latches 7-2. Level Clocking 7-3. D Latches 7-4. Edge-Triggered D Flip-Flops 7-5. Edge-Triggered JK Flip-Flops 7-6. JK Master-Slave Flip-Flop CHAPTER 8. REGISTERS AND COUNTERS 8-1. Buffer Registers 8-2. Shift Registers 8-3. Controlled Shift Registers 8-4. Ripple Counters 8-5. Synchronous Counters 8-6. Ring Counters 8-7. Other Counters 8-8. Three-State Registers 8-9. Bus-Organized Computers 9-3. RAMs Hexadecimal CHAPTER 9. MEMORIES 9-1. ROMs 9-2. PROMs and EFROMs 9-4. A Small TTL Memory 9-5. Addresses PART 2 SAP (Simple-as-Possible) Computers CHAPTER 10. SAP-1 10-1. Architecture -10-2. Instruction Set 10-3. Programming SAP-1 10-4. Fetch Cycle 10-5. Execution Cycle ip-6. The SAP-1 Microprogram 10-7. The SAP-1 Schematic Diagram 10-8. Microprogramming CHAPTER 5. BOOLEAN ALGEBRA AND KARNAUGH MAPS 5-1. Boolean Relations 5-2. Sumtpf-Products Method 5-3. Algebraic Simplification ^-4 Karnaugh Maps 5-5. Pairs. Quads, and Octets 5i6. Karnaugh Simplifications 5-7. Don't-Care Conditions CHAPTER 11. SAP-2 11-1. Bidirectional Registers 11-2. Architecture 11-3. Memory-Reference Instructions 11-4. Register Instructions 11-5. Jump and Call Instructions 11-6. Logic Instructions 11-7. Other Instructions 11-8. SAP-2 Summary CHAPTER 12. SAP-3 12-1. Programming Model 12-2. MOV and MVI 12-3. Arithmetic Instructions 12-4. Increments, Decrements, and Rotates 12-5. Logic Instructions 12-6. Arithmetic and Logic Immediates 12-7. Jump Instructions 12-8. Extended-Register Instructions 12-9. Indirect Instructions 12-10. Stack Instructions CHAPTER 18. ARITHMETIC AND FLAGS New Concepts 18-1. Microprocessors and Numbers 18-2. Arithmetic Instructions 18-3. Flag Instructions Specific Microprocessor Families 18.4 6502 Family 18-5. 6800/6808 Family 18-6. 8080/8085/Z80 Family 18-7. 8086/8088 Family P /\R ] 3 Programming Popular Microprocessors CHAPTER 13. INTRODUCTION TO MICROPROCESSORS 13-1. Computer Hardware 13-2. Definition of a Microprocessor 13-3. Some Common Uses for Microprocessors 13-4. Microprocessors Featured in This Text 13-5. Access to Microprocessors CHAPTER 14. PROGRAMMING AND LANGUAGES (4-1. Relationship between Electronics and Programming 14-2. Programming 14-3. Fundamental Premise 14-4. Flowcharts 14-5. Programming Languages 14-6. Assembly Language 14-7. Worksheets CHAPTER 15. SYSTEM OVERVIEW New Concepts 15-1. Computer Architecture 15-2. Microprocessor Architecture Specific Microprocessor Families 15-3. 6502 Family 15-4. 6800/6808 Family 15-5 . 8080/8085/Z80 Family 15-6. 8086/8088 Family CHAPTER 16. DATA TRANSFER INSTRUCTIONS New Concepts 16-1. CPU Control Instructions 16-2. Data Transfer Instructions Specific Microprocessor Families 16-3. 6502 Family 16-4. 6800/6808 Family 16-5. 8080/8085/Z80 Family 16-6. 8086/8088 Family CHAPTER 17. ADDRESSING MODES—I What Is an Addressing Mode? 17-2. The Paging Concept 17-3. Basic Addressing Modes Specific Microprocessor Families 17-4. 6502 Family 17-5 . 6800/6808 Family 17.6. 8080/8085/Z80 Family 17.7. a086/8088 Family CHAPTER 19. LOGICAL INSTRUCTIONS New Concepts 19-1. The and Instruction 19-2. The OR Instruction 19-3. The EXCLUSIVE-OR (Egr. xor) Instruction 19-4. The NOT Instruction 19-5. The NEC (NEcate) Instruction Specific Microprocessor Families 19-6. 6502 Family 19-7. 6800/6808 Family 19-8. 8080/8085/Z80 Family 19-9. 8086/8088 Family CHAPTER 20. SHIFT AND ROTATE INSTRUCTIONS New Concepts 20-1. Rotating 20-2. Shifting 20-3. An Example Specific Microprocessor Families 20-4. 6502 Family 20-5. 6800/6808 Family 20-6. 8080/8085/Z80 Family 20-7. 8086/8088 Family CHAPTER 21. ADDRESSING MODES—II New Concepts 21-1. Advanced Addressing Modes Specific Microprocessor Families 21-2. 6502 Family 21-3. 6800/6808 Family 21-4. 8080/8085/Z80 Family 21-5. 8086/8088 Family CHAPTER 22. branching AND LOOPS New Concepts 22-1. Unconditional Jumps 22-2. Conditional Branching 22-3. Compare and Test Instructions 22-4. Increment and Decrement Instructions 22-5. Nested Loops Specific Microprocessor Families 22-6. 6502 Family 22-7. 6800/6808 Family 22-8. 8080/8085/Z80 Family 22-9. 8086/8088 Family CHAPTER 23. SUBROUTINE AND STACK INSTRUCTIONS New Concepts 23-1. Stack and Stack Pointer 23-2. Branching versus Subroutines 23-3. How Do Subroutines Return? 23-4. Pushing and Popping Registers Specific Microprocessor Families 23-5. 6502 Family 23-6. 6800/6808 Family 23-7. 8080/8085/Z80 Family 24-8. 8086/8088 Family PART 4 Microprocessor Instruction Set Tables A. Expanded Table of 8085/8080 and Z80 (8080 Subset) Instructions Listed by Category 381 Mini Table of 8085/8080 and Z80 (8080 Subset) Instructions Listed by Category 410 Condensed Table of 8085/8080 and Z80 (8080) Instructions Listed by Category 415 Condensed Table of 8085/8080 and Z80 (8080 Subset) Instructions Listed by Op Code 417 Condensed Table of 8085/8080 and Z80 (8080 Subset) Instructions Listed Alphabetically by 8085/8080 Mnemonic 419 Condensed Table of 8085/8080 and Z80 (8080 Subset) Instructions Listed Alphabetically by Z80 Mnemonic 421 B. Expanded Table of 6800 Instructions Listed by Category 422 Short Table of 6800 Instructions Listed Alphabetically 434 Short Table of 6800 Instructions Listed by Category 437 Condensed Table of 6800 Instructions Listed by Category 441 Condensed Table of 6800 Instructions Listed Alphabetically 443 Condensed Table of 6800 Instructions Listed by Op Code 444 Expanded Table of 8086/8088 Instructions Listed by Category 445 Condensed Table of 8086/8088 Instructions Listed by Category 465 Condensed Table of 8086/8088 Instructions Listed Alphabetically 469 D. Expanded Table of 6502 Instructions Listed by Category 471 Short Table of 6502 Instructions Listed by Category 478 Condensed Table of 6502 Instructions Listed by Category 480 Condensed Table of 6502 Instructions Listed Alphabetically 481 Condensed Table of 6502 Instructions Listed by Op Code 482 APPENDIXES 1. The Analog Interface 2. Binary-Hexadecimal- Decimal Equivalents 3. 7400 Series TTL 4. Pinouts and Function Tables 5. SAP-1 Parts List 6. 8085instructions 7. Memory Locations: Powers of 2 8. Memory Locations: 16K and 8K Intervals 9. Memory Locations: 4K Intervals 10. Memory Locations: 2K Intervals 11. Memory Locations: IK Intervals 12. Programming Models ContentsCHAPTER 6. ARITHMETIC-LOGIC UNITS PART 1 Digital Principles 1 CHAPTER 1. NUMBER SYSTEMS AND CODES 1 1-1. Decimal Odometer 1-2. Binary Odometer 1-3. Number Codes 1-4. Why Binary Numbers Are Used 1-5. Binary-to-Decimal Conversion 1-6. Microprocessors 1-7. Decimal-to-Binary Conversion 1-8. Hexadecimal Numbers 1-9. Hexadecimal-Binary Conversions 1-10. Hexadecimal-to-Decimal Conversion 1-11. Decimal-to-Hexadecimal Conversion 1-12. BCD Numbers 1-13. The ASCII Code CHAPTER 2. GATES 2-1. Inverters 2-2. or Gates 2-4. Boolean Algebra 2-3. AND Gates CHAPTER 3. MORE LOGIC GATES 3-1. NOR Gates 3-2. De Morgan's First Theorem 3-3. NAND Gates 3-4. De Morgan's Second Theorem 3-5. EXCLUSIVE-OR Gates 3-6. The Controlled Inverter 3-7. exclusive-nor Gates CHAPTER 4. TTL CIRCUITS 4-1. Digital Integrated Circuits 4-2. 7400 Devices 4-3. TTL Characteristics 4-4. TTL Overview 4-5. AND-OR-iNVERT Gates 4-6. Open-Collector Gates 4-7. Multiplexers 6-1. Binary Addition 6-2. Binary Subtraction 6-3. Half Adders 6-4. Full Adders 6-5. Binary Adders 6-6. Signed Binary NOitibers 6-7. 2's Complement 6-8. 2's-CompIement Adder-Subtracter CHAPTER 7. FLIP-FLOPS 7-1. Latches 7-2. Level Clocking 7-3. D Latches 7-4. Edge-Triggered D Flip-Flops 7-5. Edge-Triggered JK Flip-Flops 7-6. JK Master-Slave Flip-Flop CHAPTER 8. REGISTERS AND COUNTERS 8-1. Buffer Registers 8-2. Shift Registers 8-3. Controlled Shift Registers 8-4. Ripple Counters 8-5. Synchronous Counters 8-6. Ring Counters 8-7. Other Counters 8-8. Three-State Registers 8-9. Bus-Organized Computers 9-3. RAMs Hexadecimal CHAPTER 9. MEMORIES 9-1. ROMs 9-2. PROMs and EFROMs 9-4. A Small TTL Memory 9-5. Addresses PART 2 SAP (Simple-as-Possible) Computers CHAPTER 10. SAP-1 10-1. Architecture -10-2. Instruction Set 10-3. Programming SAP-1 10-4. Fetch Cycle 10-5. Execution Cycle ip-6. The SAP-1 Microprogram 10-7. The SAP-1 Schematic Diagram 10-8. Microprogramming CHAPTER 5. BOOLEAN ALGEBRA AND KARNAUGH MAPS 5-1. Boolean Relations 5-2. Sumtpf-Products Method 5-3. Algebraic Simplification ^-4 Karnaugh Maps 5-5. Pairs. Quads, and Octets 5i6. Karnaugh Simplifications 5-7. Don't-Care Conditions CHAPTER 11. SAP-2 11-1. Bidirectional Registers 11-2. Architecture 11-3. Memory-Reference Instructions 11-4. Register Instructions 11-5. Jump and Call Instructions 11-6. Logic Instructions 11-7. Other Instructions 11-8. SAP-2 Summary CHAPTER 12. SAP-3 12-1. Programming Model 12-2. MOV and MVI 12-3. Arithmetic Instructions 12-4. Increments, Decrements, and Rotates 12-5. Logic Instructions 12-6. Arithmetic and Logic Immediates 12-7. Jump Instructions 12-8. Extended-Register Instructions 12-9. Indirect Instructions 12-10. Stack Instructions CHAPTER 18. ARITHMETIC AND FLAGS New Concepts 18-1. Microprocessors and Numbers 18-2. Arithmetic Instructions 18-3. Flag Instructions Specific Microprocessor Families 18.4 6502 Family 18-5. 6800/6808 Family 18-6. 8080/8085/Z80 Family 18-7. 8086/8088 Family P /\R ] 3 Programming Popular Microprocessors CHAPTER 13. INTRODUCTION TO MICROPROCESSORS 13-1. Computer Hardware 13-2. Definition of a Microprocessor 13-3. Some Common Uses for Microprocessors 13-4. Microprocessors Featured in This Text 13-5. Access to Microprocessors CHAPTER 14. PROGRAMMING AND LANGUAGES (4-1. Relationship between Electronics and Programming 14-2. Programming 14-3. Fundamental Premise 14-4. Flowcharts 14-5. Programming Languages 14-6. Assembly Language 14-7. Worksheets CHAPTER 15. SYSTEM OVERVIEW New Concepts 15-1. Computer Architecture 15-2. Microprocessor Architecture Specific Microprocessor Families 15-3. 6502 Family 15-4. 6800/6808 Family 15-5 . 8080/8085/Z80 Family 15-6. 8086/8088 Family CHAPTER 16. DATA TRANSFER INSTRUCTIONS New Concepts 16-1. CPU Control Instructions 16-2. Data Transfer Instructions Specific Microprocessor Families 16-3. 6502 Family 16-4. 6800/6808 Family 16-5. 8080/8085/Z80 Family 16-6. 8086/8088 Family CHAPTER 17. ADDRESSING MODES—I What Is an Addressing Mode? 17-2. The Paging Concept 17-3. Basic Addressing Modes Specific Microprocessor Families 17-4. 6502 Family 17-5 . 6800/6808 Family 17.6. 8080/8085/Z80 Family 17.7. a086/8088 Family CHAPTER 19. LOGICAL INSTRUCTIONS New Concepts 19-1. The and Instruction 19-2. The OR Instruction 19-3. The EXCLUSIVE-OR (Egr. xor) Instruction 19-4. The NOT Instruction 19-5. The NEC (NEcate) Instruction Specific Microprocessor Families 19-6. 6502 Family 19-7. 6800/6808 Family 19-8. 8080/8085/Z80 Family 19-9. 8086/8088 Family CHAPTER 20. SHIFT AND ROTATE INSTRUCTIONS New Concepts 20-1. Rotating 20-2. Shifting 20-3. An Example Specific Microprocessor Families 20-4. 6502 Family 20-5. 6800/6808 Family 20-6. 8080/8085/Z80 Family 20-7. 8086/8088 Family CHAPTER 21. ADDRESSING MODES—II New Concepts 21-1. Advanced Addressing Modes Specific Microprocessor Families 21-2. 6502 Family 21-3. 6800/6808 Family 21-4. 8080/8085/Z80 Family 21-5. 8086/8088 Family CHAPTER 22. branching AND LOOPS New Concepts 22-1. Unconditional Jumps 22-2. Conditional Branching 22-3. Compare and Test Instructions 22-4. Increment and Decrement Instructions 22-5. Nested Loops Specific Microprocessor Families 22-6. 6502 Family 22-7. 6800/6808 Family 22-8. 8080/8085/Z80 Family 22-9. 8086/8088 Family CHAPTER 23. SUBROUTINE AND STACK INSTRUCTIONS New Concepts 23-1. Stack and Stack Pointer 23-2. Branching versus Subroutines 23-3. How Do Subroutines Return? 23-4. Pushing and Popping Registers Specific Microprocessor Families 23-5. 6502 Family 23-6. 6800/6808 Family 23-7. 8080/8085/Z80 Family 24-8. 8086/8088 Family PART 4 Microprocessor Instruction Set Tables A. Expanded Table of 8085/8080 and Z80 (8080 Subset) Instructions Listed by Category 381 Mini Table of 8085/8080 and Z80 (8080 Subset) Instructions Listed by Category 410 Condensed Table of 8085/8080 and Z80 (8080) Instructions Listed by Category 415 Condensed Table of 8085/8080 and Z80 (8080 Subset) Instructions Listed by Op Code 417 Condensed Table of 8085/8080 and Z80 (8080 Subset) Instructions Listed Alphabetically by 8085/8080 Mnemonic 419 Condensed Table of 8085/8080 and Z80 (8080 Subset) Instructions Listed Alphabetically by Z80 Mnemonic 421 B. Expanded Table of 6800 Instructions Listed by Category 422 Short Table of 6800 Instructions Listed Alphabetically 434 Short Table of 6800 Instructions Listed by Category 437 Condensed Table of 6800 Instructions Listed by Category 441 Condensed Table of 6800 Instructions Listed Alphabetically 443 Condensed Table of 6800 Instructions Listed by Op Code 444 Expanded Table of 8086/8088 Instructions Listed by Category 445 Condensed Table of 8086/8088 Instructions Listed by Category 465 Condensed Table of 8086/8088 Instructions Listed Alphabetically 469 D. Expanded Table of 6502 Instructions Listed by Category 471 Short Table of 6502 Instructions Listed by Category 478 Condensed Table of 6502 Instructions Listed by Category 480 Condensed Table of 6502 Instructions Listed Alphabetically 481 Condensed Table of 6502 Instructions Listed by Op Code 482 APPENDIXES 1. The Analog Interface 2. Binary-Hexadecimal- Decimal Equivalents 3. 7400 Series TTL 4. Pinouts and Function Tables 5. SAP-1 Parts List 6. 8085instructions 7. Memory Locations: Powers of 2 8. Memory Locations: 16K and 8K Intervals 9. Memory Locations: 4K Intervals 10. Memory Locations: 2K Intervals 11. Memory Locations: IK Intervals 12. Programming Models Contents
650			_aComputer _910454
942			_cWB16
999			_c1615 _d1615