TY  - BOOK
AU  - Vahid, Frank
TI  - Embedded system design: a unified hardware/ software introduction
SN  - 9788126508372 (alk. paper)
U1  - 005.256 
PY  - 2007///
CY  - New York
PB  - Springer
KW  - Embedded Computer Systems
KW  - Automotive Computers
N1  - Includes bibliographical references; CHAPTER 1: Introduction
1.1 Embedded Systems Overview
1.2 Design Challenge — Optimizing Design Metrics
Common Design Metrics
The Time-to-Market Design Metric
The NRE and Unit Cost Design Metrics
The Performance Design Metric
1.3 Processor Technology
General-Purpose Processors — Software
Single-Purpose Processors — Hardware
Application-Specific Processors
1.4 IC Technology
Full-CustomATLSI
Semicustom ASIC (Gate Array and Standard Cell)
PLD
Trends
1.5 Design Technology
Compilation/Synthesis
Libraries/IP
Test/Verification
More Productivity Improvers
Trends
1.6 Trade-ofFs
Design Productivity Gap
1.7 Summary and Book Outline
1.8 References and Further Reading
1.9 Exercises
CHAPTER 2; Custom Single-Purpose Processors. Hardware
2.1 Introduction
2.2 Combinational Logic
Transistors and Logic Gates
Basic Combinational Logic Design
RT-Level Combinational Components
2.3 Sequential Logic
Flip-Flops
RT-Level Sequential Components
Sequential Logic Design
2.4 Custom Single-Purpose Processor Design
2.5 RT-Level Custom Single-Purpose Processor Design
2.6 Optimizing Custom Single-Purpose Processors
Optimizing the Original Program
Optimizing the FSMD.
Optimizing the Datapath
Optimizing the FSM
2.7 Summary
2.8 References and Further Reading
2.9 Exercises
CHAPTERS; General-Purpose Processors: Software
3.1 Introduction
3.2 Basic Architecture
Datapath
Control Unit -
Memory
3.3 Operation
Instruction Execution
Pipelining
Superscalar and VLIW Architectures ' ,
3.4 Programmer's View
Instruction Set
Program and Data Memory Space
Registers
I/O
Interrupts
Example: Assembly-Language Programming of Device Drivers
Operating System
3.5 Development Environment
Design Flow and Tools
Example: Instruction-Set Simulator for a Simple Processor
Testing and Debugging
3.6 Application-Specific Instruction-Set Processors (ASIPs)
Microcontrollers
Digital Signal Processors (DSP)
Less-General ASIP Environments
3.7 Selecting a Microprocessor
3.8 General-Purpose Processor Design
3.9 Summary
3.10 References and Further Reading
3.11 Exercises
CHAPTER 4: Standard Single-Purpose Processors: Peripherals
4.1 Introduction
4.2 Timers, Counters, and Watchdog Timers
Timers and Counters
Example: Reaction Timer
Watchdog Timers
Example: ATM Timeout Using a Watchdog Timer
4.3 UART
4.4 Pulse Width Modulators
Overview
Example: Controlling a DC Motor Using a PWM
4.5 LCD Controllers
Overview
Example: LCD Initialization
4.6 Keypad Controllers
4.7 Stepper Motor Controllers
Overview
Example; Using a Stepper Motor Driver
Example: Controlling a Stepper Motor Directly
4.8 Analog-to-Digital Converters
Example: Successive Approximation
4.9 Real-Time Clocks
4.10 Summary
4.11 References and f'urther Reading
4.12 Exercises
CHAPTER 5: Meisfiory
5.1 Introduction
5.2 Memory Write Ability and Storage Permanence
Write Ability
Storage Permanence
Trade-offs
5.3 Common Memory Types
Introduction to "Read-Only" Memory — ROM
Mask-Programmed ROM
OTP ROM — One-Time Programmable ROM
EPROM — Erasable Programmable ROM
EEPROM — Electrically Erasable Programmable ROM
Flash Memory
Introduction to Read-Write Memory — RAM
SRAM — Static RAM
DRAM — Dynamic RAM
PSRAM — Pseudo-Static RAM
NVRAM — Nonvolatile RAM
Example: HM6264 and 27C256 RAM/ROM Devices
Example: TC55V2325FF-100 Memory Device
5.4 Composing Memory
5.5 Memory Hierarchy and Cache
Cache Mapping Techniques
Cache-Replacement Policy
Cache Write Techniques
Cache Impact on System Performance
5.6 Advanced RAM
The Basic DRAM
Fast Page Mode DRAM (FPM DRAM)
Extended Data Out DRAM (EDO DRAM)
Synchronous (S) and Enhanced Synchronous (ES) DRAM
Rambus DRAM (RDRAM)
DRAM Integration Problem
Memory Management Unit (MMU)
5.7 Summary
5.8 References and Further Reading
5.9 Exercises
CHAPTER 6: Interfacing
6.1 Introduction
6.2 Communication Basics
Basic Terminology
Basic Protocol Concepts
Example; The ISA Bus Protocol — Memory Access
6.3 Microprocessor Interfacing: I/O Addressing
Port and Bus-Based I/O
Memory-Mapped I/O and Standard I/O
Example: The ISA Bus Protocol — Standard I/O
Example: A Basic Memory Protocol
• Example: A Complex Memory Protocol
6.4 Microprocessor Interfacing: Interrupts
6.5 Microprocessor Interfacing: Direct Memory Access
Example: DMA I/O and the ISA Bus Protocol
6.6 Arbitration
Priority Arbiter
Daisy-Chain Arbitration
Network-Oriented Arbitration Methods
Example: Vectored Interrupt Using an Interrupt table
6.7 Multilevel Bus Architectures
6.8 Advanced Communication Principles
Parallel Communication
Serial Communication
Wireless Communication
Layering
Error Detection and Correction
6.9 Serial Protocols
I^C
GAN
FireWire
USB
6.10 Parallel Protocols
PCI Bus
ARM Bus
6.11 Wireless Protocols
IrDA
Bluetooth
IEEE802.il
6.12 Summary
6.13 References and Further Reading
6.14 Exercises
CHAPTER?: Digital Camera Example -
7.1 Introduttion
7.2 Introduction to a Simple Digital Camera
User's Perspective
Designer's Perspective
7.3 Requirements Specification
Nonfimctional Requirements
Informal Functional Specification
Refined Functional- Specification
7.4 Design
Implementation I: Microcontroller Alone
Implementation 2: Microcontroller and CCDPP
Implementation 3: Microcontroller and CCDPP/Fixed-Point DCT
Implementation 4: Microcontroller and CCDPP/DCT
7.5 Summary
7.6 References and Further Reading
7.7 Exercises
CHAPTER 8: State Machine and Concurrent Process Models
8.1 Introduction
8.2 Models vs. Languages, Text vs. Graphics
Models vs. Languages
Textual Languages vs. Graphical Languages
8.3 An Introductory Example
8.4 A Basic State Machine Model: Finite-State Machines
8.5 Finite-State Machine with Datapath Model: FSMD
8.6 Using State Machines
Describing a System as a State Machiiie
Comparing State Machine and Sequential Program Models
Capturing State Machines in Sequential Programming Language
8.7 HCFSM and the Statecharts Language
8.8 Program-State Machine Model (PSM)
8.9 The Role of an Appropriate Model and Language
8.10 Concurrent Process Model
8.11 Concurrent Processes
Process Create and Terminate
Process Suspend and Resume
Process Join
8.12 Communication among Processes
Shared Memory
Message Passing
8.13 Synchronization among Processes
Condition Variables
Monitors
8.14 Implementation
Creating and Terminating Processes
Suspending and Resuming Processes
Joining a Process
Scheduling Processes
8.15 Dataflow Model
8.16 Real-Time Systems
Windows CE
QNX
8.17 Summary
8.18 References and Further Reading
8.19 Exercises
CHAPTER 9: Control Systems
9.1 Introduction
9.2 Open-Loop and Closed-Loop Control Systems
Overview
A First Example; An Open-Loop Automobile Cruise Controller
A Second Example: A Closed-Loop Automobile Cruise Controller
9.3 General Control Systems and PID Controllers
Control Objectives
Modeling Real Physical Systems
Controller Design
9.4 Software Coding of a PID Controller
9.5 PID Tuning
9.6 Practical Issues Related to Computer-Based Control
Quantization and Overflow Effects
Aliasing
Computation Delay
9.7 Benefits of Computer-Based Control Implementations
Repeatability, Reproducability, and Stability
Programmability
9.8 Summary
9.9 References and Further Reading
9.10 Exercises
CHAPTER 10: IC Technology
10.1 Introduction
10.2 Full-Custom (VLSI) IC Technology
10.3 Semi-Custom (ASIC) IC Technology
Gate Array Semi-Custom IC Technology
Standard Cell Semi-Custom IC Technology
10.4 Programmable Logic Device (PLD) IC Technology
10.5 Summary
10.6 References and Further Reading
10.7 Exercises
CHAPTER 11: Design Technology
11.1 Introduction
11.2 Automation: Synthesis
"Going up": The Parallel Evolution of Compilation and Synthesis
Synthesis Levels
Logic Synthesis
Register-Transfer Synthesis
Behavioral Synthesis
System Synthesis and Hardware/Software Codesign
Temporal and Spatial Thinking
11.3 Verification: Hardware/Software Co-Simulation
Formal Verification and Simulation
Simulation Speed
Hardware-Software Co-Simulation
Emulators
11.4 Reuse: Intellectual Property Cores
Hard, soft and firm cores
New Challenges Posed by Cores to Processor Providers
New Challenges Posed by Cores to Processor Users
11.5 Design Process Models
11.6 Summary
11.7 Book Summary
11.8 References and Further Reading
11.9 Exercises
APPENDIX A: Online Resources
A. 1 Introduction
A.2 Summary of the ESD Web Page
A. 3 Lab Resources
Chapter 2
Chapter 3
Chapter 4
Chapter 5
Chapter 6
Chapter 7
A.4 About the Book Cover
Outdoors
Indoors
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