VLSI-SoC: Internet of Things Foundations/

By: ClaesenMaterial type: TextTextPublication details: New York: Springer, ISBN: 978-3-319-25279-7Online resources: Click here to access online
Contents:
Dynamic Programming-Based Lifetime Reliability Optimization in Networks-on-Chip Liang Wang, Xiaohang Wang, Terrence Mak Efficient Utilization of Test Elevators to Reduce Test Time in 3D-ICs Sreenivaas S. Muthyala, Nur A. Touba Design and Optimization of Multiple-Mesh Clock Network Jinwook Jung, Dongsoo Lee, Youngsoo Shin Energy-Efficient Partitioning of Hybrid Caches in Multi-core Architecture Dongwoo Lee, Kiyoung Choi Interval Arithmetic and Self Similarity Based Subthreshold Leakage Optimization in RTL Datapaths Shilpa Pendyala, Srinivas Katkoori 8T-SRAM cell with Improved Read and Write Margins in 65 nm CMOS Technology Farshad Moradi, Mohammad Tohidi, Behzad Zeinali, Jens K. Madsen On the Co-simulation of SystemC with QEMU and OVP Virtual Platforms Alessandro Lonardi, Graziano Pravadelli Statistical Evaluation of Digital Techniques for ΣΔΣΔ ADC BIST Matthieu Dubois, Haralampos-G. Stratigopoulos, Salvador Mir, Manuel J. Barragan A Parallel MCMC-Based MIMO Detector: VLSI Design and Algorithm Dominik Auras, Uwe Deidersen, Rainer Leupers, Gerd Ascheid Real-Time Omnidirectional Imaging System with Interconnected Network of Cameras Kerem Seyid, Ömer Çogal, Vladan Popovic, Hossein Afshari, Alexandre Schmid, Yusuf Leblebici Transmission Channel Noise Aware Energy Effective LDPC Decoding Thomas Marconi, Christian Spagnol, Emanuel Popovici, Sorin Cotofana Laser-Induced Fault Effects in Security-Dedicated Circuits Vincent Beroulle, Philippe Candelier, Stephan De Castro, Giorgio Di Natale, Jean-Max Dutertre, Marie-Lise Flottes et al.
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Dynamic Programming-Based Lifetime Reliability Optimization in Networks-on-Chip
Liang Wang, Xiaohang Wang, Terrence Mak

Efficient Utilization of Test Elevators to Reduce Test Time in 3D-ICs
Sreenivaas S. Muthyala, Nur A. Touba

Design and Optimization of Multiple-Mesh Clock Network
Jinwook Jung, Dongsoo Lee, Youngsoo Shin

Energy-Efficient Partitioning of Hybrid Caches in Multi-core Architecture
Dongwoo Lee, Kiyoung Choi

Interval Arithmetic and Self Similarity Based Subthreshold Leakage Optimization in RTL Datapaths
Shilpa Pendyala, Srinivas Katkoori

8T-SRAM cell with Improved Read and Write Margins in 65 nm CMOS Technology
Farshad Moradi, Mohammad Tohidi, Behzad Zeinali, Jens K. Madsen

On the Co-simulation of SystemC with QEMU and OVP Virtual Platforms
Alessandro Lonardi, Graziano Pravadelli

Statistical Evaluation of Digital Techniques for ΣΔΣΔ ADC BIST
Matthieu Dubois, Haralampos-G. Stratigopoulos, Salvador Mir, Manuel J. Barragan

A Parallel MCMC-Based MIMO Detector: VLSI Design and Algorithm
Dominik Auras, Uwe Deidersen, Rainer Leupers, Gerd Ascheid

Real-Time Omnidirectional Imaging System with Interconnected Network of Cameras
Kerem Seyid, Ömer Çogal, Vladan Popovic, Hossein Afshari, Alexandre Schmid, Yusuf Leblebici

Transmission Channel Noise Aware Energy Effective LDPC Decoding
Thomas Marconi, Christian Spagnol, Emanuel Popovici, Sorin Cotofana

Laser-Induced Fault Effects in Security-Dedicated Circuits
Vincent Beroulle, Philippe Candelier, Stephan De Castro, Giorgio Di Natale, Jean-Max Dutertre, Marie-Lise Flottes et al.

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