Embedded system design: a unified hardware/ software introduction / (Record no. 2778)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 09201cam a22001814a 4500 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9788126508372 (alk. paper) |
| 040 ## - CATALOGING SOURCE | |
| Transcribing agency | CUS |
| 082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 005.256 |
| Item number | VAH/E |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Vahid, Frank |
| 245 10 - TITLE STATEMENT | |
| Title | Embedded system design: a unified hardware/ software introduction / |
| Statement of responsibility, etc. | Frank Vahid and Tony Givargis |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication, distribution, etc. | New York : |
| Name of publisher, distributor, etc. | Springer, |
| Date of publication, distribution, etc. | 2007. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | xvi, 444 p. |
| Other physical details | ill. ; |
| Dimensions | 25 cm. |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE | |
| Bibliography, etc | Includes bibliographical references. |
| 505 ## - FORMATTED CONTENTS NOTE | |
| Formatted contents note | CHAPTER 1: Introduction<br/>1.1 Embedded Systems Overview<br/>1.2 Design Challenge — Optimizing Design Metrics<br/>Common Design Metrics<br/>The Time-to-Market Design Metric<br/>The NRE and Unit Cost Design Metrics<br/>The Performance Design Metric<br/>1.3 Processor Technology<br/>General-Purpose Processors — Software<br/>Single-Purpose Processors — Hardware<br/>Application-Specific Processors<br/>1.4 IC Technology<br/>Full-CustomATLSI<br/>Semicustom ASIC (Gate Array and Standard Cell)<br/>PLD<br/>Trends<br/>1.5 Design Technology<br/>Compilation/Synthesis<br/>Libraries/IP<br/>Test/Verification<br/>More Productivity Improvers<br/>Trends<br/>1.6 Trade-ofFs<br/>Design Productivity Gap<br/>1.7 Summary and Book Outline<br/>1.8 References and Further Reading<br/>1.9 Exercises<br/>CHAPTER 2; Custom Single-Purpose Processors. Hardware<br/>2.1 Introduction<br/>2.2 Combinational Logic<br/>Transistors and Logic Gates<br/>Basic Combinational Logic Design<br/>RT-Level Combinational Components<br/>2.3 Sequential Logic<br/>Flip-Flops<br/>RT-Level Sequential Components<br/>Sequential Logic Design<br/>2.4 Custom Single-Purpose Processor Design<br/>2.5 RT-Level Custom Single-Purpose Processor Design<br/>2.6 Optimizing Custom Single-Purpose Processors<br/>Optimizing the Original Program<br/>Optimizing the FSMD.<br/>Optimizing the Datapath<br/>Optimizing the FSM<br/>2.7 Summary<br/>2.8 References and Further Reading<br/>2.9 Exercises<br/>CHAPTERS; General-Purpose Processors: Software<br/>3.1 Introduction<br/>3.2 Basic Architecture<br/>Datapath<br/>Control Unit -<br/>Memory<br/>3.3 Operation<br/>Instruction Execution<br/>Pipelining<br/>Superscalar and VLIW Architectures ' ,<br/>3.4 Programmer's View<br/>Instruction Set<br/>Program and Data Memory Space<br/>Registers<br/>I/O<br/>Interrupts<br/>Example: Assembly-Language Programming of Device Drivers<br/>Operating System<br/>3.5 Development Environment<br/>Design Flow and Tools<br/>Example: Instruction-Set Simulator for a Simple Processor<br/>Testing and Debugging<br/>3.6 Application-Specific Instruction-Set Processors (ASIPs)<br/>Microcontrollers<br/>Digital Signal Processors (DSP)<br/>Less-General ASIP Environments<br/>3.7 Selecting a Microprocessor<br/>3.8 General-Purpose Processor Design<br/>3.9 Summary<br/>3.10 References and Further Reading<br/>3.11 Exercises<br/>CHAPTER 4: Standard Single-Purpose Processors: Peripherals<br/>4.1 Introduction<br/>4.2 Timers, Counters, and Watchdog Timers<br/>Timers and Counters<br/>Example: Reaction Timer<br/>Watchdog Timers<br/>Example: ATM Timeout Using a Watchdog Timer<br/>4.3 UART<br/>4.4 Pulse Width Modulators<br/>Overview<br/>Example: Controlling a DC Motor Using a PWM<br/>4.5 LCD Controllers<br/>Overview<br/>Example: LCD Initialization<br/>4.6 Keypad Controllers<br/>4.7 Stepper Motor Controllers<br/>Overview<br/>Example; Using a Stepper Motor Driver<br/>Example: Controlling a Stepper Motor Directly<br/>4.8 Analog-to-Digital Converters<br/>Example: Successive Approximation<br/>4.9 Real-Time Clocks<br/>4.10 Summary<br/>4.11 References and f'urther Reading<br/>4.12 Exercises<br/>CHAPTER 5: Meisfiory<br/>5.1 Introduction<br/>5.2 Memory Write Ability and Storage Permanence<br/>Write Ability<br/>Storage Permanence<br/>Trade-offs<br/>5.3 Common Memory Types<br/>Introduction to "Read-Only" Memory — ROM<br/>Mask-Programmed ROM<br/>OTP ROM — One-Time Programmable ROM<br/>EPROM — Erasable Programmable ROM<br/>EEPROM — Electrically Erasable Programmable ROM<br/>Flash Memory<br/>Introduction to Read-Write Memory — RAM<br/>SRAM — Static RAM<br/>DRAM — Dynamic RAM<br/>PSRAM — Pseudo-Static RAM<br/>NVRAM — Nonvolatile RAM<br/>Example: HM6264 and 27C256 RAM/ROM Devices<br/>Example: TC55V2325FF-100 Memory Device<br/>5.4 Composing Memory<br/>5.5 Memory Hierarchy and Cache<br/>Cache Mapping Techniques<br/>Cache-Replacement Policy<br/>Cache Write Techniques<br/>Cache Impact on System Performance<br/>5.6 Advanced RAM<br/>The Basic DRAM<br/>Fast Page Mode DRAM (FPM DRAM)<br/>Extended Data Out DRAM (EDO DRAM)<br/>Synchronous (S) and Enhanced Synchronous (ES) DRAM<br/>Rambus DRAM (RDRAM)<br/>DRAM Integration Problem<br/>Memory Management Unit (MMU)<br/>5.7 Summary<br/>5.8 References and Further Reading<br/>5.9 Exercises<br/>CHAPTER 6: Interfacing<br/>6.1 Introduction<br/>6.2 Communication Basics<br/>Basic Terminology<br/>Basic Protocol Concepts<br/>Example; The ISA Bus Protocol — Memory Access<br/>6.3 Microprocessor Interfacing: I/O Addressing<br/>Port and Bus-Based I/O<br/>Memory-Mapped I/O and Standard I/O<br/>Example: The ISA Bus Protocol — Standard I/O<br/>Example: A Basic Memory Protocol<br/>• Example: A Complex Memory Protocol<br/>6.4 Microprocessor Interfacing: Interrupts<br/>6.5 Microprocessor Interfacing: Direct Memory Access<br/>Example: DMA I/O and the ISA Bus Protocol<br/>6.6 Arbitration<br/>Priority Arbiter<br/>Daisy-Chain Arbitration<br/>Network-Oriented Arbitration Methods<br/>Example: Vectored Interrupt Using an Interrupt table<br/>6.7 Multilevel Bus Architectures<br/>6.8 Advanced Communication Principles<br/>Parallel Communication<br/>Serial Communication<br/>Wireless Communication<br/>Layering<br/>Error Detection and Correction<br/>6.9 Serial Protocols<br/>I^C<br/>GAN<br/>FireWire<br/>USB<br/>6.10 Parallel Protocols<br/>PCI Bus<br/>ARM Bus<br/>6.11 Wireless Protocols<br/>IrDA<br/>Bluetooth<br/>IEEE802.il<br/>6.12 Summary<br/>6.13 References and Further Reading<br/>6.14 Exercises<br/>CHAPTER?: Digital Camera Example -<br/>7.1 Introduttion<br/>7.2 Introduction to a Simple Digital Camera<br/>User's Perspective<br/>Designer's Perspective<br/>7.3 Requirements Specification<br/>Nonfimctional Requirements<br/>Informal Functional Specification<br/>Refined Functional- Specification<br/>7.4 Design<br/>Implementation I: Microcontroller Alone<br/>Implementation 2: Microcontroller and CCDPP<br/>Implementation 3: Microcontroller and CCDPP/Fixed-Point DCT<br/>Implementation 4: Microcontroller and CCDPP/DCT<br/>7.5 Summary<br/>7.6 References and Further Reading<br/>7.7 Exercises<br/>CHAPTER 8: State Machine and Concurrent Process Models<br/>8.1 Introduction<br/>8.2 Models vs. Languages, Text vs. Graphics<br/>Models vs. Languages<br/>Textual Languages vs. Graphical Languages<br/>8.3 An Introductory Example<br/>8.4 A Basic State Machine Model: Finite-State Machines<br/>8.5 Finite-State Machine with Datapath Model: FSMD<br/>8.6 Using State Machines<br/>Describing a System as a State Machiiie<br/>Comparing State Machine and Sequential Program Models<br/>Capturing State Machines in Sequential Programming Language<br/>8.7 HCFSM and the Statecharts Language<br/>8.8 Program-State Machine Model (PSM)<br/>8.9 The Role of an Appropriate Model and Language<br/>8.10 Concurrent Process Model<br/>8.11 Concurrent Processes<br/>Process Create and Terminate<br/>Process Suspend and Resume<br/>Process Join<br/>8.12 Communication among Processes<br/>Shared Memory<br/>Message Passing<br/>8.13 Synchronization among Processes<br/>Condition Variables<br/>Monitors<br/>8.14 Implementation<br/>Creating and Terminating Processes<br/>Suspending and Resuming Processes<br/>Joining a Process<br/>Scheduling Processes<br/>8.15 Dataflow Model<br/>8.16 Real-Time Systems<br/>Windows CE<br/>QNX<br/>8.17 Summary<br/>8.18 References and Further Reading<br/>8.19 Exercises<br/>CHAPTER 9: Control Systems<br/>9.1 Introduction<br/>9.2 Open-Loop and Closed-Loop Control Systems<br/>Overview<br/>A First Example; An Open-Loop Automobile Cruise Controller<br/>A Second Example: A Closed-Loop Automobile Cruise Controller<br/>9.3 General Control Systems and PID Controllers<br/>Control Objectives<br/>Modeling Real Physical Systems<br/>Controller Design<br/>9.4 Software Coding of a PID Controller<br/>9.5 PID Tuning<br/>9.6 Practical Issues Related to Computer-Based Control<br/>Quantization and Overflow Effects<br/>Aliasing<br/>Computation Delay<br/>9.7 Benefits of Computer-Based Control Implementations<br/>Repeatability, Reproducability, and Stability<br/>Programmability<br/>9.8 Summary<br/>9.9 References and Further Reading<br/>9.10 Exercises<br/>CHAPTER 10: IC Technology<br/>10.1 Introduction<br/>10.2 Full-Custom (VLSI) IC Technology<br/>10.3 Semi-Custom (ASIC) IC Technology<br/>Gate Array Semi-Custom IC Technology<br/>Standard Cell Semi-Custom IC Technology<br/>10.4 Programmable Logic Device (PLD) IC Technology<br/>10.5 Summary<br/>10.6 References and Further Reading<br/>10.7 Exercises<br/>CHAPTER 11: Design Technology<br/>11.1 Introduction<br/>11.2 Automation: Synthesis<br/>"Going up": The Parallel Evolution of Compilation and Synthesis<br/>Synthesis Levels<br/>Logic Synthesis<br/>Register-Transfer Synthesis<br/>Behavioral Synthesis<br/>System Synthesis and Hardware/Software Codesign<br/>Temporal and Spatial Thinking<br/>11.3 Verification: Hardware/Software Co-Simulation<br/>Formal Verification and Simulation<br/>Simulation Speed<br/>Hardware-Software Co-Simulation<br/>Emulators<br/>11.4 Reuse: Intellectual Property Cores<br/>Hard, soft and firm cores<br/>New Challenges Posed by Cores to Processor Providers<br/>New Challenges Posed by Cores to Processor Users<br/>11.5 Design Process Models<br/>11.6 Summary<br/>11.7 Book Summary<br/>11.8 References and Further Reading<br/>11.9 Exercises<br/>APPENDIX A: Online Resources<br/>A. 1 Introduction<br/>A.2 Summary of the ESD Web Page<br/>A. 3 Lab Resources<br/>Chapter 2<br/>Chapter 3<br/>Chapter 4<br/>Chapter 5<br/>Chapter 6<br/>Chapter 7<br/>A.4 About the Book Cover<br/>Outdoors<br/>Indoors |
| 650 #0 - SUBJECT | |
| Keyword | Embedded Computer Systems |
| 650 #0 - SUBJECT | |
| Keyword | Automotive Computers |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | General Books |
| Withdrawn status | Lost status | Damaged status | Not for loan | Home library | Current library | Shelving location | Date acquired | Full call number | Accession number | Date last seen | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Central Library, Sikkim University | Central Library, Sikkim University | General Book Section | 14/06/2016 | 005.256 VAH/E | P35843 | 14/06/2016 | General Books |