Computer organization and design: the hardware software interface / (Record no. 2749)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 07313nam a22001815i 4500 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9788131222744 (pb) |
| 040 ## - CATALOGING SOURCE | |
| Transcribing agency | CUS |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 005.275 |
| Item number | PAT/C |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Patterson, David. |
| 245 10 - TITLE STATEMENT | |
| Title | Computer organization and design: the hardware software interface / |
| Statement of responsibility, etc. | David Patterson and John Hennessy. |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 4th ed. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication, distribution, etc. | Haryana : |
| Name of publisher, distributor, etc. | Elsevier , |
| Date of publication, distribution, etc. | 2010. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | xxv, 689 p. |
| Other physical details | ill. ; |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE | |
| Bibliography, etc | includes index |
| 505 ## - FORMATTED CONTENTS NOTE | |
| Formatted contents note | 1.1 Introduction<br/>1.2 Below Your Program<br/>1.3 Under the Covers<br/>1.4 Performance<br/>1.5 The Power Wall<br/>1.6 The Sea Change: The Switch from Uni processors to<br/>Multiprocessors<br/>1.7 Real Stuff: Manufacturing and Benchmarking the AMD<br/>Opteron X4<br/>1.8 Fallacies and Pitfalls<br/>1.9 Concluding Remarks<br/>1.10 Historical Perspective and Further Reading<br/>1.11 Exercises<br/>2.1 Introduction<br/>2.2 Operations of the Computer Hardware<br/>2.3 Operands of the Computer Hardware<br/>2.4 Signed and Unsigned Numbers<br/>2.5 Representing Instructions in the Computer<br/>2.6 Logical Operations<br/>2.7 Instructions for Making Decisions<br/>2.8 Supporting Procedures in Computer Hardware<br/>2.9 Communicating with People<br/>2.10 ARM Addressing for 32-Bit Immediates and<br/>More Complex Addressing Modes<br/>2.11 Parallelism and Instructions: Synchronization<br/>2.12 Translating and Starting a Program<br/>2.13 AC Sort Example to Put It AH Together<br/>2.14 Arrays versus Pointers<br/>2.15 Advanced Material: Compiling C and Interpreting Java<br/>2.16 Real Stufif: MIPS Instructions<br/>2.17 Real Stuff; x86 Instructions<br/>2.18 Fallacies and Pitfalls<br/>2.19 Concluding Remarks<br/>2.20 Historical Perspective and Further Reading<br/>2.21 Exercises<br/>3.1 Introduction<br/>3.2 Addition and Subtraction<br/>3.3 Multiplication<br/>3.4 Division<br/>3.5 Floating Point<br/>3.6 Parallelism and Computer Arithmetic: Associativity<br/>3.7 Real Stuff: Floating Point in the x86<br/>3.8 Fallacies and Pitfalls<br/>3.9 Concluding Remarks<br/>3.10 Historical Perspective and Fiuther Reading<br/>3.11 Exercises<br/>4.1 Introduction<br/>4.2 Logic Design Conventions<br/>4.3 Building a Datapath<br/>4.4 A Simple Implementation Scheme<br/>4.5 An Overview of Pipelining<br/>4.6 Pipelined Datapath and Control<br/>4.7 Data Hazards: Forwarding versus Stalling<br/>4.8 Control Hazards<br/>4.9 Exceptions<br/>4.10 Parallelism and Advanced Instruction-Level Parallelism<br/>4.11 Real Stuff; the AMD Opteron X4 (Barcelona) Pipeline<br/>4.12 Advanced Topic: an Introduction to Digital Design<br/>Using a Hardware Design Language to Describe and Model a Pipeline<br/>and More Pipelining Illustrations<br/>4.13 Fallacies and Pitfalls<br/>4.14 Concluding Remarks<br/>4.15 Historical Perspective and Further Reading<br/>4.16 Exercises<br/>Large and Fast: Exploiting Memory Hierarchy<br/>5.1 Introduction<br/>5.2 The Basics of Caches<br/>5.3 Measuring and Improving Cache Performance<br/>5.4 Virtual Memory<br/>5.5 A Common Framework for Memory Hierarchies<br/>5.6 Virtual Machines<br/>5.7 Using a Finite-State Machine to Control a Simple Cache<br/>5.8 Parallelism and Memory Hierarchies: Cache Coherence<br/>5.9 Advanced Material: Implementing Cache Controllers<br/>5.10 Real Stuffi the AMD Opteron X4 (Barcelona) and Intel Nehalem<br/>Memory Hierarchies<br/>5.11 Fallacies and Pithdls<br/>5.12 Concluding Remarks<br/>5.13 Historical Perspective and Further Reading<br/>5.14 Exercises<br/>Storage and Other I/O Topics<br/>6.1 Introduction<br/>6.2 Dependability, Reliability, and Availability<br/>6.3 Disk Storage<br/>6.4 Flash Storage<br/>6.5 Connecting Processors, Memory, and I/O Devices<br/>6.6 Interfacing I/O Devices to the Processor, Memory, and<br/>Operating System<br/>6.7 I/O Performance Measures: Examples from Disk and File Systems<br/>6.8 Designing an I/O System<br/>6.9 Parallelism and 1/0: Redundant Arrays of lne3q)ensive Disks<br/>6.10 Real Stuffi Sun Fire x4150 Server<br/>6.11 Advanced Topics: Networks<br/>6.12 Fallacies and Pitfalls<br/>6.13 Concluding Remarks<br/>6.14 Historical Perspective and Further Reading<br/>6.15 Exercises<br/>Muitlcores, Multiprocessors, and Clusters<br/>7.1 Introduction<br/>7.2 The Difficulty of Creating Parallel Processing Programs<br/>7.3 Shared Memory Multiprocessors<br/>7.4 Clusters and Other Message-Passing Multiprocessors<br/>7.5 Hardware Multithreading<br/>7.6 SISD, MIMD, SIMD, SPMD, and Vector<br/>7.7 Introduction to Graphics Processing Units<br/>7.8 Introduction to Multiprocessor Network Topologies<br/>7.9 Multiprocessor Benchmarks<br/>7.10 Roofline; A Simple Performance Model<br/>7.11 Real Stuff: Benchmarking Four Multicores Using the<br/>Roofline Model<br/>7.12 Fallacies and Pitfalls<br/>7.13 Concluding Remarks<br/>7.14 Historical Perspective and Further Reading<br/>7.15 Exercises<br/>Graphics and Computing GPUs<br/>A.1 Introduction<br/>A.2 GPU System Architectures<br/>A.3 Scalable Parallelism - Programming GPUs<br/>A.4 Multithreaded Multiprocessor Architecture<br/>A.5 Parallel Memory System G.6 Floating Point<br/>A.6 Floating Point Arithmetic<br/>A.7 Real Stuff; The NVIDIA GeForce 8800<br/>A.8 Real Stuff; Mapping Applications to GPUs<br/>A.9 Fallacies and Pitfalls<br/>A. 10 Concluding Remarks<br/>A. 11 Historical Perspective and Further Reading<br/>ARM and Thumb Assembier instructions<br/>Bl.l Using This Appendix<br/>BI.2 Syntax<br/>B1.3 Alphabetical List of ARM and Thumb Instructions<br/>B1.4 ARM Assembler Quick Reference<br/>B1.5 GNU Assembler Quick Reference<br/>ARM and Thumb Instruction Encodings<br/>B2.1 ARM Instruction Set Encodings<br/>B2.2 Thumb Instruction Set Encodings<br/>B2.3 Program Status Registers<br/>Instruction Cycie Timings<br/>B3.1 Using the Instruction Set Cycle Timing Tables<br/>B3.2 ARM7TDMI Instruction Cycle Timings<br/>B3.3 ARM9TDMI Instruction Cycle Timings<br/>B3.4 StrongARMlInstruction Cycle Timings<br/>B3.5 ARM9E Instruction Cycle Timings<br/>B3.6 ARMlOE Instruction Cycle Timings<br/>B3.7 Intel XScale Instruction Cycle Timings<br/>B3.8 ARM 11 Cycle Timings<br/>The Basics of Logic Design<br/>C.l Introduction<br/>C.2 Gates, Truth Tables, and Logic Equations<br/>C.3 Combinational Logic<br/>C.4 Using a Hardware Description Language<br/>C.5 Constructing a Basic Arithmetic Logic Unit<br/>C.6 Faster Addition: Carry Lookahead<br/>C.7 Clocks<br/>C.8 Memory Elements: Flip-Flops, Latches, and Registers<br/>C.9 Memory Elements: SRAMs and DRAMs<br/>C.IO Finite-State Machines<br/>C.ll Timing Methodologies<br/>C.l2 Field Programmable Devices<br/>C.l3 Concluding Remarks<br/>C.14 Exercises<br/>Mapping Controi to Hardware<br/>D.l Introduction<br/>D.2 Implementing Combinational Control Units<br/>D.3 Implementing Finite-State Machine Control<br/>D.4 Implementing the Next-State Function with a Sequencer<br/>D.5 Translating a Microprogram to Hardware<br/>D.6 Concluding Remarks<br/>D.7 Exercises<br/>Section 2.15 Compiling C and Interpreting Java<br/>Section 4.12 An Introduction to Digital Design Using a Hardware<br/>Design Language to Describe and Model a Pipeline and<br/>More Pipelining Illustrations<br/>Section 5.9 Implementing Cache Controllers<br/>Section 6.11 Networks<br/>HISTORICAL PERSPECTIVES & FURTHER<br/>READING<br/>Chapter 1 Computer Abstractions and Technology: Section<br/>Chapter 2 Instructions: Language of the Computer: Section<br/>Chapter 3 Arithmetic for Computers: Section<br/>Chapter 4 The Processor: Section<br/>Chapter 5 Large and Fast: Exploiting Memory Hierarchy: Section<br/>Chapter 6 Storage and Other I/O Topics: Section<br/>Chapter 7 Multicores, Multiprocessors, and Clusters: Section<br/>Appendix A Graphics and Computing CPUs: Section A.<br/>TUTORIALS<br/>VHDL<br/>Verilog<br/>SOFT W A R E<br/>ary<br/>Xilinx FPGA Design, Simulation and Synthesis Software<br/>QEMU http://www.nongnu.org/qemu/about.htmler<br/> Reading |
| 650 ## - SUBJECT | |
| Keyword | Computer Programming |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | General Books |
| Withdrawn status | Lost status | Damaged status | Not for loan | Home library | Current library | Shelving location | Date acquired | Full call number | Accession number | Date last seen | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Central Library, Sikkim University | Central Library, Sikkim University | General Book Section | 14/06/2016 | 005.275 PAT/C | P33352 | 14/06/2016 | General Books |