ARm system developer`s guide: designing and optimizing system software / (Record no. 2664)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 04182nam a2200157 4500 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 978818147646 (pb) |
| 040 ## - CATALOGING SOURCE | |
| Transcribing agency | CUS |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 005.12 |
| Item number | SLO/A |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Sloss, Andrew N. |
| 245 ## - TITLE STATEMENT | |
| Title | ARm system developer`s guide: designing and optimizing system software / |
| Statement of responsibility, etc. | Andrew N. Sloss, Dominic Symes and Chris Wright |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication, distribution, etc. | New Delhi : |
| Name of publisher, distributor, etc. | Elsevier , |
| Date of publication, distribution, etc. | 2004. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | xiii, 689 p. |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE | |
| Bibliography, etc | includes appendix, index |
| 505 ## - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Chapter<br/>Chapter<br/>Chapter<br/>ARM Embedded Systems<br/>1.1 The RISC Design Philosophy<br/>1.2 The ARM Design Philosophy<br/>1.3 Embedded System Hardware<br/>1.4 Embedded System Software<br/>1.5 Summary<br/>ARM PROCESSOR Fundamentals<br/>2.1 Registers<br/>2.2 Current Program Status Register<br/>2.3 Pipeline<br/>2.4 Exceptions, Interrupts, and the Vector Table<br/>2.5 Core Extensions<br/>2.6 Architecture Revisions<br/>2.7 ARM Processor Families<br/>2.8 Summary<br/>Introduction to the ARM Instruction set<br/>3.1 Data Processing Instructions<br/>3.2 Branch Instructions<br/>3.3 Load-Store Instrufctions<br/>3.4 Software Interrupt Instruction<br/>3.5 Program Status Register Instructions<br/>3.6 Loading Constants<br/>3.7 ARMvSE Extensions<br/>3.8 Conditional Execution<br/>3.9 Summary<br/>Chapter<br/>CHAPTER<br/>Introduction to the Thumb Instruction Set<br/>4.1 Thumb Register Usage<br/>4.2 ARM-Thumb Interworking<br/>4.3 Other Branch Instructions<br/>4.4 Data Processing Instructions<br/>4.5 Single-Register Load-Store Instructions<br/>4.6 Multiple-Register Load-Store Instructions<br/>4.7 Stack Instructions<br/>4.8 Software Interrupt Instruction<br/>4.9 Summary<br/>Efficient C Programming<br/>5.1 Overview of C CompUers and Optimization<br/>5.2 Basic C Data Types<br/>5.3 C Looping Structures<br/>5.4 Register Allocation<br/>5.5 Function Calls<br/>5.6 Pointer Aliasing<br/>5.7 Structure Arrangement<br/>5.8 Bit-fields<br/>5.9 Unaligned Data and Endianness<br/>5.10 Division<br/>5.11 Floatingpoint<br/>5.12 Inline Functions and Inline Assembly<br/>5.13 Portability Issues<br/>5.14 Summary<br/>6 Writing and optimizing ARM Assembly code<br/>6.1<br/>6.2<br/>6.3<br/>6.4<br/>6.5<br/>6.6<br/>6.7<br/>6.8<br/>Writing Assembly Code<br/>Profiling and Cycle Counting<br/>Instruction Scheduling<br/>Register Allocation<br/>Conditional Execution<br/>Looping Constructs<br/>Bit Manipulation<br/>Efficient Switches<br/>Chapter<br/>Chapter<br/>8<br/>Chapter<br/>Chapter<br/>6.9 Handling Unaligned Data<br/>6.10 Summary<br/>Optimized Primitives<br/>7.1 Double-Precision Integer Multiplication<br/>7.2 Integer Normalization and Count Leading Zeros<br/>7.3 Division<br/>7.4 Square Roots<br/>7.5 Transcendental Functions: log, exp, sin, cos<br/>7.6 Endian Reversal and Bit Operations<br/>7.7 Saturated and Rounded Arithmetic<br/>7.8 Random Number Generation<br/>7.9 Summary<br/>Digital Signal Processing<br/>8.1 Representing a Digital Signal<br/>8.2 Introduction to DSP on the ARM<br/>8.3 FIR filters<br/>8.4 IIR Filters<br/>8.5 The Discrete Fourier Transform<br/>8.6 Summary<br/>Exception and Interrupt Handling<br/>9.1 Exception Handling<br/>9.2 Interrupts<br/>9.3 Interrupt Handling Schemes<br/>9.4 Summary<br/>10<br/>Firmware<br/>10.1 Firmware and Bootloader<br/>10.2 Example: Sandstone<br/>10.3 Summary<br/>CHAPTER<br/>11<br/>Chapter<br/>12<br/>CHAPTER<br/>CHAPTER<br/>14<br/>Embedded operating Systems<br/>11.1 Fundamental Components<br/>11.2 Example: Simple Little Operating System<br/>11.3 Summary<br/>Caches<br/>12.1 The Memory Hierarchy and Cache Memory<br/>12.2 Cache Architecture<br/>12.3 Cache Policy<br/>12.4 Coprocessor 15 and Caches<br/>12.5 Flushing and Cleaning Cache Memory<br/>12.6 Cache Lockdown<br/>12.7 Caches and Software Performance<br/>12.8 Sununary<br/>13 mbmqry protection units<br/>13 1 Protected Regions<br/>13^2 Initializing the MPU, Caches, and Wnte Buffer<br/>13.3 Demonstration of an MPU system<br/>13.4 Summary<br/>14.1 Moving from an MPU to an MMU<br/>14^2 How Virtual Memory Works<br/>14.3 Details of the ARM MMU<br/>14.4 Page Tables<br/>14 5 The Translation Lookaside Buffer<br/>1^6 Domains and Memory Access Permission<br/>14 7 The Caches and Write Buffer<br/>U.S Coprocessor 15 and MMU Configuration<br/>14 9 The Fast Context Switch Extension _ . „<br/>l^io DemonstrarionrASmaHVirtuJMemorySystem<br/>14.11 The Demonstration as mmuSLOS<br/>14.12 Summary<br/>Chapter<br/>15<br/>The Future of the architecture<br/>BY John Rayfieud<br/>15.1 Advanced DSP and SIMD Support in ARMv6<br/>15.2 System and Multiprocessor Support Additions to ARMv6<br/>15.3 ARMv6 Implementations<br/>15.4 Future Technologies beyond ARMv6<br/>15.5 Summary |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | General Books |
| Withdrawn status | Lost status | Damaged status | Not for loan | Home library | Current library | Shelving location | Date acquired | Full call number | Accession number | Date last seen | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Central Library, Sikkim University | Central Library, Sikkim University | General Book Section | 13/06/2016 | 005.12 SLO/A | P18483 | 13/06/2016 | General Books |