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Computer Architecture and Organization (Record no. 2123)

MARC details
000 -LEADER
fixed length control field	03365pam a2200241 a 4500
003 - CONTROL NUMBER IDENTIFIER
control field	OSt
005 - DATE AND TIME OF LATEST TRANSACTION
control field	20230311163422.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field	211029b xxu\|\|\|\|\| \|\|\|\| 00\| 0 eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number	0070273669 (pb)
040 ## - CATALOGING SOURCE
Transcribing agency	CUS
082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number	004.22
Item number	HAY/C
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name	Hayes, John P
9 (RLIN)	17490
245 10 - TITLE STATEMENT
Title	Computer Architecture and Organization
250 ## - EDITION STATEMENT
Edition statement	3rd ed.
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT)
Place of publication, distribution, etc.	New York :
Name of publisher, distributor, etc.	McGraw-Hill,
Date of publication, distribution, etc.	1988.
300 ## - PHYSICAL DESCRIPTION
Extent	xv, 702 p.
Dimensions	25 cm.
Other physical details	ill. ;
440 #0 - SERIES STATEMENT/ADDED ENTRY--TITLE
Title	McGraw-Hill series in computer organization and architecture
9 (RLIN)	17491
500 ## - GENERAL NOTE
General note	"Intended primarily as a text for computer science and electrical engineering courses at the advanced undergraduate or beginning graduate levels"--P. xiii.
505 ## - FORMATTED CONTENTS NOTE
Formatted contents note	Computing and Computers<br/>1.1 The Nature of Computing<br/>1.1.1 The Elements of Computers / 1.1.2 Limitations<br/>of Computers<br/>1.2 The Evolution Oif Computers<br/>1.2.1 The Mechanical Era / 1.2.2 Electronic Computers /<br/>1.2.3 The Later Generations<br/>IJ The VLSI Era<br/>1.3.1 Integrated Circuits / 1.3.2 Processor Architecture /<br/>1.3.3 System Architecture<br/>1.4 Summary<br/>1.5 Problems<br/>1.6 References<br/>Design Methodology<br/>2.1 System Design<br/>2.LI System Representation / 2.1.2 Design Process /<br/>2.1.3 The Gate Level<br/>2.2 The Register Level<br/>2.2.1 Register-Level Components / 2.2.2 Programmable<br/>Logic Devices / 2.2.3 Register-Level Design<br/>2.3 The Processor Level<br/>2.3.1 Processor-Level Components / 2.3.2 Processor-Level<br/>Design<br/>2.4 Summary<br/>2.5 Problems<br/>2.6 References<br/>Processor Basics<br/>3.1 CPU Organization<br/>3.1.1 Fundamentals / 3.1.i Additional Features<br/>3.2 Data Representation<br/>3.2.1 Basic Formats / 3.2.2 Fixed-Point Numbers /<br/>3.2.3 Floating-Point Numbers<br/>3.3 Instruction Sets<br/>3.3.1 Instruction Formats / 3.3.2 Instruction Types /<br/>3.3.3 Programming Considerations<br/>3.4 Summary<br/>3.5 Problems<br/>3.6 References<br/>Datapath Design<br/>4.1 Fixed-Point Arithmetic<br/>4.1.1 Addition and Subtraction / 4.1.2 Multiplication /<br/>4.1.3 Division<br/>4.2 Arithmetic-Logic Units<br/>4.2.1 Combinational ALUs / 4.2.2 Sequential ALUs<br/>4.3 Advanced Topics<br/>4.3.1 Floating-Point Arithmetic / 4.3.2 Pipeline Processing<br/>4.4 Summary<br/>4.5 Problems<br/>4.6 References<br/>Control Design<br/>5.1 Basic Concepts<br/>5.1.1 Introduction / 5.1.2 Hardwired Control /<br/>5.1.3 Design Examples<br/>5.2 Microprogrammed Control<br/>5.2.1 Basic Concepts / 5.2.2 Multiplier Control Unit /<br/>5.2.3 CPU Control Unit<br/>5.3 Pipeline Control<br/>5.3.1 Instruction Pipelines / 5.3.2 Pipeline Performance /<br/>5.3.3 Superscalar Processing<br/>5.4 Summary<br/>5.5 Problems<br/>5.6 References<br/>Memory Organization<br/>6.1 Memory Techiiology<br/>6.1.1 Memory Device'Characteristics / 6.1.2 Random-<br/>Access Memories / 6.1.3 SeriaUAccess Memories<br/>6.2 Memory Systems<br/>6.2.1 Multilevel Memories / 6.2.2 Address Translation /<br/>6.2.3 Memory Allocation<br/>6.3 Caches<br/>6.3.1 Main Features / 6.3.2 Address Mapping /<br/>6.3.3 Structure versus Performance<br/>6.4 Summary<br/>6.5 Problems<br/>6.6 References<br/>System Organization<br/>7.1 Communication Methods<br/>7.1.1 Basic Concepts / 7.1.2 Bus Control<br/>7.2 10 And System Control<br/>7.2.1 Programmed 10 / 7.2.2 DMA and Interrupts /<br/>7.2.310 Processors / 7.2.4 Operating Systems<br/>7.3 Parallel Processing<br/>7.3.1 Processor-Level Parallelism / 7.3.2 Multiprocessors /<br/>7.3.3 Fault Tolerance
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element	Computer architecture.
9 (RLIN)	8559
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element	Electronic Digital Computers
General subdivision	Design and construction.
9 (RLIN)	17492
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type	General Books
Source of classification or shelving scheme

Holdings
Home library	Current library	Shelving location	Date acquired	Total Checkouts	Full call number	Barcode	Date last seen	Date last checked out	Koha item type	Price effective from
Central Library, Sikkim University	Central Library, Sikkim University	General Book Section	01/06/2016	1	004.22 HAY/C	P33200	14/07/2018	14/07/2018	General Books
Central Library, Sikkim University	Central Library, Sikkim University	General Book Section	01/06/2016	2	004.22 HAY/C	P33203	20/06/2019	20/06/2019	General Books
Central Library, Sikkim University	Central Library, Sikkim University	General Book Section	02/06/2016	2	004.22 HAY/C	P33201	07/06/2019	07/06/2019	General Books	02/06/2016
Central Library, Sikkim University	Central Library, Sikkim University		29/08/2016		004.22 HAY/C	P33202	29/08/2016		General Books	29/08/2016