Computer systems design and architecture / (Record no. 1726)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 04368cam a22001934a 4500 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 0130484407 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9780130484406 |
| 040 ## - CATALOGING SOURCE | |
| Transcribing agency | CUS |
| 082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 004.22 |
| Item number | HEU/C |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Heuring, Vincent P. |
| 245 10 - TITLE STATEMENT | |
| Title | Computer systems design and architecture / |
| Statement of responsibility, etc. | Vincent P. Heuring, Harry F. Jordan a contri and T.G. Venkatesh |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 2nd ed. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication, distribution, etc. | Upper Saddle River, N.J. : |
| Name of publisher, distributor, etc. | Pearson/Prentice Hall, |
| Date of publication, distribution, etc. | 2004. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | xvi, 592 p |
| Dimensions | 25 cm. |
| Other physical details | ill. ; |
| 505 ## - FORMATTED CONTENTS NOTE | |
| Formatted contents note | CHAPTER 1 The General Purpose Machine<br/>The General Purpose Machine 2<br/>The User's View 3<br/>The Machine/Assembly Language Programmer's View 5<br/>The Computer Architect's View 11<br/>The Computer System Logic Designer's View 16<br/>Historical Perspective 19<br/>Trends and Research 23<br/>Approach of the Text 24<br/>Summary 25<br/>Bibliography 26<br/>Exercises 26<br/>1.1<br/>1.2<br/>1.3<br/>1.4<br/>1.5<br/>1.6<br/>1.7<br/>1.8<br/>CHAPTER 2 Machines, Machine Langui^es, and Digital Logic<br/>Classification of Computers and Their Instructions 30<br/>Computer Instruction Sets 32<br/>Informal Description of the Simple RISC Computer, SRC 47<br/>Formal Description of SRC Using Register Transfer Notation, RTN<br/>Describing Addressing Modes with RTN 64<br/>Register Transfers and Logic Circuits: From Behavior to Hardware<br/>Summary 77<br/>Bibliography 78<br/>Exercises 79<br/>2.1<br/>2.2<br/>2.3<br/>2.4<br/>2.5<br/>2.6<br/>55<br/>66<br/>CHAPTER 3 Some Real Machines<br/>3.1<br/>3.2<br/>Machine Characteristics and Performance<br/>RISC versus CISC 88<br/>84<br/>3.3 A CISC Microprocessor: The Motorola MC68000 93<br/>3.4 A RISC Architecture: The SPARC 117<br/>3.5 More CISC and RISC Processors 132<br/>3.6 Digital Signal Processors 137<br/>Summary 141<br/>Bibliography 142<br/>Exercises 143<br/>CHAPTER 4 Processor Design<br/>4.1 The Design Process 148<br/>4.2 A 1-Bus Microarchitecture for the SRC 149<br/>4.3 Data Path Implementation 154<br/>4.4 Logic Design for the 1-Bus SRC 155<br/>4.5 The Control Unit 167<br/>4.6 The 2-and 3-Bus Processor Designs 175<br/>4.7 The Machine Reset 181<br/>4.8 Machine Exceptions 183<br/>4.9 Microprogramming 191<br/>Summary 205<br/>Bibliography 206<br/>Exercises 206<br/>chapter 5 Processor Design—^Exploiting Parallelism<br/>5.1 Pipelining Overview 212<br/>5.2 Design of Linear Pipeline 214<br/>5!3 Design of Static and Dynamic Multifunction Non-Linear Pipeline<br/>5.4 Design of Instruction Pipeline 239<br/>5.5 Pipeline Hazards 256<br/>5.6 Instruction-Level Parallelism 280<br/>Summary 303<br/>Bibliography 303<br/>Exercises 304<br/>CHAPTER 6 Computer Arithmetic and the Arithmetic Unit<br/>6.1 Number Systems and Radix Conversion 311<br/>6.2 Fixed-Point Arithmetic 322<br/>6.3 Seminumeric Aspects of ALU Design 356<br/>6.4 Floating-Point Arithmetic 362<br/>Summary 371<br/>Bibliography 371<br/>Exercises 372<br/>CHAPTER 7 Memory System Design<br/>7.1 Introduction: The Components of the Memory System 378<br/>7.2 RAM Structure: The Logic Designer's Perspective 381<br/>7.3 Memory Boards and Modules 397<br/>7.4 Memory Hierarchy 416<br/>7.5 The Cache 422<br/>7.6 Virtual Memory 444<br/>7.7 The Memory Subsystem in the Computer 465<br/>Summary 467<br/>Bibliography 468<br/>Exercises 468<br/>CHAPTER 8 Input aud Output<br/>8.1 The I/O Subsystem 474<br/>8.2 Programmed I/O 477<br/>8.3 I/O Interrupts 486<br/>8.4 Direct Memory Access (DMA) 494<br/>'8.5 I/O Data Format Change and Error Control 497<br/>Summary 503<br/>Bibliography 504<br/>Exercises 504<br/>CHAPTER 9 System Software Architectures<br/>9.1 Operating System 507<br/>9.2 Compilers, Loaders, and Linkers 521<br/>9.3 Assembly and Assemblers 525<br/>Summary 535<br/>Bibliography 535<br/>CHAPTER 10 Peripheral Devices<br/>10.1 Magnetic Disk Drives 538<br/>10.2 Improving Disk System Performance and Reliability 547<br/>10.3 Other Mass Storage Devices 549<br/>10.4 Display Devices 550<br/>10.5 Printers 558<br/>10.6 Input Devices 560<br/>10.7 Interfacing to the Analog World 561<br/>Summary 565<br/>Bibliography 566<br/>Exercises 566<br/>CHAPTER 11 Conununications, Networking, and the Internet<br/>11.1 Computer to Computer Data Communications 570<br/>11.2 Serial Data Communications Protocols 578<br/>11.3 Local Area Networks 584<br/>11.4 Modern Serial Buses: USB and FireWire 587<br/>11.5 The Internet 591<br/>Summary 601<br/>Bibliography 602<br/>Exercises 603<br/>CHAPTER 12 Parallel Processing<br/>12.1 Taxonomy of Parallel Architectures 606<br/>12.2 Vector Supercomputers 607<br/>12.3 SIMD Array Processors 609<br/>12.4 Shared Memory Multiprocessor 611<br/>12.5 Interconnection Networks (IN) 612<br/>12.6 The Systolic Array Processors 619<br/>Bibliography 625<br/>Exercises 625 |
| 650 #0 - SUBJECT | |
| Keyword | System Design. |
| 650 #0 - SUBJECT | |
| Keyword | Computer Architecture. |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | General Books |
| Withdrawn status | Lost status | Damaged status | Not for loan | Home library | Current library | Shelving location | Date acquired | Full call number | Accession number | Date last seen | Date last checked out | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Central Library, Sikkim University | Central Library, Sikkim University | General Book Section | 31/05/2016 | 004.22 HEU/C | P18721 | 17/03/2020 | 17/03/2020 | General Books |