Normal view MARC view ISBD view

Digital computer electronics (Record no. 1615)

MARC details
000 -LEADER
fixed length control field	15599nam a2200169 4500
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number	9780074622353 (pb)
040 ## - CATALOGING SOURCE
Transcribing agency	CUS
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number	004
Item number	MAL/D
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name	Malvino, Albert Paul
245 ## - TITLE STATEMENT
Title	Digital computer electronics
Statement of responsibility, etc.	Albert Paul Malvino and Jerald A. Brown
250 ## - EDITION STATEMENT
Edition statement	3rd ed.
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT)
Place of publication, distribution, etc.	New Delhi :
Name of publisher, distributor, etc.	Tata Mcgraw hill ,
Date of publication, distribution, etc.	1995.
300 ## - PHYSICAL DESCRIPTION
Extent	522 p.
Other physical details	ill. ;
505 ## - FORMATTED CONTENTS NOTE
Formatted contents note	CHAPTER 6. ARITHMETIC-LOGIC UNITS<br/>PART 1<br/>Digital Principles 1<br/>CHAPTER 1. NUMBER SYSTEMS AND<br/>CODES 1<br/>1-1. Decimal Odometer 1-2. Binary Odometer<br/>1-3. Number Codes 1-4. Why Binary Numbers Are<br/>Used 1-5. Binary-to-Decimal Conversion<br/>1-6. Microprocessors 1-7. Decimal-to-Binary<br/>Conversion 1-8. Hexadecimal Numbers<br/>1-9. Hexadecimal-Binary Conversions<br/>1-10. Hexadecimal-to-Decimal Conversion<br/>1-11. Decimal-to-Hexadecimal Conversion<br/>1-12. BCD Numbers 1-13. The ASCII Code<br/>CHAPTER 2. GATES<br/>2-1. Inverters 2-2. or Gates<br/>2-4. Boolean Algebra<br/>2-3. AND Gates<br/>CHAPTER 3. MORE LOGIC GATES<br/>3-1. NOR Gates 3-2. De Morgan's First Theorem<br/>3-3. NAND Gates 3-4. De Morgan's Second Theorem<br/>3-5. EXCLUSIVE-OR Gates 3-6. The Controlled<br/>Inverter 3-7. exclusive-nor Gates<br/>CHAPTER 4. TTL CIRCUITS<br/>4-1. Digital Integrated Circuits 4-2. 7400 Devices<br/>4-3. TTL Characteristics 4-4. TTL Overview<br/>4-5. AND-OR-iNVERT Gates 4-6. Open-Collector Gates<br/>4-7. Multiplexers<br/>6-1. Binary Addition 6-2. Binary Subtraction<br/>6-3. Half Adders 6-4. Full Adders 6-5. Binary<br/>Adders 6-6. Signed Binary NOitibers 6-7. 2's<br/>Complement 6-8. 2's-CompIement Adder-Subtracter<br/>CHAPTER 7. FLIP-FLOPS<br/>7-1. Latches 7-2. Level Clocking 7-3. D Latches<br/>7-4. Edge-Triggered D Flip-Flops 7-5. Edge-Triggered<br/>JK Flip-Flops 7-6. JK Master-Slave Flip-Flop<br/>CHAPTER 8. REGISTERS AND<br/>COUNTERS<br/>8-1. Buffer Registers 8-2. Shift Registers<br/>8-3. Controlled Shift Registers 8-4. Ripple Counters<br/>8-5. Synchronous Counters 8-6. Ring Counters<br/>8-7. Other Counters 8-8. Three-State Registers<br/>8-9. Bus-Organized Computers<br/>9-3. RAMs<br/>Hexadecimal<br/>CHAPTER 9. MEMORIES<br/>9-1. ROMs 9-2. PROMs and EFROMs<br/>9-4. A Small TTL Memory 9-5.<br/>Addresses<br/>PART 2<br/>SAP (Simple-as-Possible)<br/>Computers<br/>CHAPTER 10. SAP-1<br/>10-1. Architecture -10-2. Instruction Set<br/>10-3. Programming SAP-1 10-4. Fetch Cycle<br/>10-5. Execution Cycle ip-6. The SAP-1<br/>Microprogram 10-7. The SAP-1 Schematic Diagram<br/>10-8. Microprogramming<br/>CHAPTER 5. BOOLEAN ALGEBRA AND<br/>KARNAUGH MAPS<br/>5-1. Boolean Relations 5-2. Sumtpf-Products Method<br/>5-3. Algebraic Simplification ^-4 Karnaugh Maps<br/>5-5. Pairs. Quads, and Octets 5i6. Karnaugh<br/>Simplifications 5-7. Don't-Care Conditions<br/>CHAPTER 11. SAP-2<br/>11-1. Bidirectional Registers 11-2. Architecture<br/>11-3. Memory-Reference Instructions 11-4. Register<br/>Instructions 11-5. Jump and Call Instructions<br/>11-6. Logic Instructions 11-7. Other Instructions<br/>11-8. SAP-2 Summary<br/>CHAPTER 12. SAP-3<br/>12-1. Programming Model 12-2. MOV and MVI<br/>12-3. Arithmetic Instructions 12-4. Increments,<br/>Decrements, and Rotates 12-5. Logic Instructions<br/>12-6. Arithmetic and Logic Immediates 12-7. Jump<br/>Instructions 12-8. Extended-Register Instructions<br/>12-9. Indirect Instructions 12-10. Stack Instructions<br/>CHAPTER 18. ARITHMETIC AND FLAGS<br/>New Concepts 18-1. Microprocessors and Numbers<br/>18-2. Arithmetic Instructions 18-3. Flag Instructions<br/>Specific Microprocessor Families 18.4 6502 Family<br/>18-5. 6800/6808 Family 18-6. 8080/8085/Z80 Family<br/>18-7. 8086/8088 Family<br/>P /\R ] 3<br/>Programming Popular<br/>Microprocessors<br/>CHAPTER 13. INTRODUCTION TO<br/>MICROPROCESSORS<br/>13-1. Computer Hardware<br/>13-2. Definition of a Microprocessor<br/>13-3. Some Common Uses for Microprocessors<br/>13-4. Microprocessors Featured in This Text<br/>13-5. Access to Microprocessors<br/>CHAPTER 14. PROGRAMMING AND<br/>LANGUAGES<br/>(4-1. Relationship between Electronics and Programming<br/>14-2. Programming 14-3. Fundamental Premise<br/>14-4. Flowcharts 14-5. Programming Languages<br/>14-6. Assembly Language 14-7. Worksheets<br/>CHAPTER 15. SYSTEM OVERVIEW<br/>New Concepts 15-1. Computer Architecture<br/>15-2. Microprocessor Architecture<br/>Specific Microprocessor Families<br/>15-3. 6502 Family 15-4. 6800/6808 Family<br/>15-5 . 8080/8085/Z80 Family 15-6. 8086/8088 Family<br/>CHAPTER 16. DATA TRANSFER<br/>INSTRUCTIONS<br/>New Concepts 16-1. CPU Control Instructions<br/>16-2. Data Transfer Instructions<br/>Specific Microprocessor Families<br/>16-3. 6502 Family 16-4. 6800/6808 Family<br/>16-5. 8080/8085/Z80 Family 16-6. 8086/8088 Family<br/>CHAPTER 17. ADDRESSING MODES—I<br/>What Is an Addressing Mode?<br/>17-2. The Paging Concept<br/>17-3. Basic Addressing Modes<br/>Specific Microprocessor Families 17-4. 6502 Family<br/>17-5 . 6800/6808 Family 17.6. 8080/8085/Z80 Family<br/>17.7. a086/8088 Family<br/>CHAPTER 19. LOGICAL INSTRUCTIONS<br/>New Concepts 19-1. The and Instruction<br/>19-2. The OR Instruction<br/>19-3. The EXCLUSIVE-OR (Egr. xor) Instruction<br/>19-4. The NOT Instruction<br/>19-5. The NEC (NEcate) Instruction<br/>Specific Microprocessor Families 19-6. 6502 Family<br/>19-7. 6800/6808 Family 19-8. 8080/8085/Z80 Family<br/>19-9. 8086/8088 Family<br/>CHAPTER 20. SHIFT AND ROTATE<br/>INSTRUCTIONS<br/>New Concepts 20-1. Rotating 20-2. Shifting<br/>20-3. An Example Specific Microprocessor Families<br/>20-4. 6502 Family 20-5. 6800/6808 Family<br/>20-6. 8080/8085/Z80 Family 20-7. 8086/8088 Family<br/>CHAPTER 21. ADDRESSING MODES—II<br/>New Concepts 21-1. Advanced Addressing Modes<br/>Specific Microprocessor Families 21-2. 6502 Family<br/>21-3. 6800/6808 Family 21-4. 8080/8085/Z80 Family<br/>21-5. 8086/8088 Family<br/>CHAPTER 22. branching AND LOOPS<br/>New Concepts 22-1. Unconditional Jumps<br/>22-2. Conditional Branching<br/>22-3. Compare and Test Instructions<br/>22-4. Increment and Decrement Instructions<br/>22-5. Nested Loops<br/>Specific Microprocessor Families 22-6. 6502 Family<br/>22-7. 6800/6808 Family 22-8. 8080/8085/Z80 Family<br/>22-9. 8086/8088 Family<br/>CHAPTER 23. SUBROUTINE AND STACK<br/>INSTRUCTIONS<br/>New Concepts 23-1. Stack and Stack Pointer<br/>23-2. Branching versus Subroutines<br/>23-3. How Do Subroutines Return?<br/>23-4. Pushing and Popping Registers<br/>Specific Microprocessor Families 23-5. 6502 Family<br/>23-6. 6800/6808 Family 23-7. 8080/8085/Z80 Family<br/>24-8. 8086/8088 Family<br/>PART 4<br/>Microprocessor Instruction<br/>Set Tables<br/>A.<br/>Expanded Table of 8085/8080 and Z80 (8080 Subset)<br/>Instructions Listed by Category 381<br/>Mini Table of 8085/8080 and Z80 (8080 Subset)<br/>Instructions Listed by Category 410<br/>Condensed Table of 8085/8080 and Z80 (8080)<br/>Instructions Listed by Category 415<br/>Condensed Table of 8085/8080 and Z80 (8080 Subset)<br/>Instructions Listed by Op Code 417<br/>Condensed Table of 8085/8080 and Z80 (8080 Subset)<br/>Instructions Listed Alphabetically by 8085/8080<br/>Mnemonic 419<br/>Condensed Table of 8085/8080 and Z80 (8080 Subset)<br/>Instructions Listed Alphabetically by Z80 Mnemonic<br/>421<br/>B.<br/>Expanded Table of 6800 Instructions Listed by Category<br/>422<br/>Short Table of 6800 Instructions Listed Alphabetically<br/>434<br/>Short Table of 6800 Instructions Listed by Category<br/>437<br/>Condensed Table of 6800 Instructions Listed by Category<br/>441<br/>Condensed Table of 6800 Instructions Listed<br/>Alphabetically 443<br/>Condensed Table of 6800 Instructions Listed by Op Code<br/>444<br/>Expanded Table of 8086/8088 Instructions Listed by<br/>Category 445<br/>Condensed Table of 8086/8088 Instructions Listed by<br/>Category 465<br/>Condensed Table of 8086/8088 Instructions Listed<br/>Alphabetically 469<br/>D.<br/>Expanded Table of 6502 Instructions Listed by Category<br/>471<br/>Short Table of 6502 Instructions Listed by Category<br/>478<br/>Condensed Table of 6502 Instructions Listed by Category<br/>480<br/>Condensed Table of 6502 Instructions Listed<br/>Alphabetically 481<br/>Condensed Table of 6502 Instructions Listed by Op Code<br/>482<br/>APPENDIXES<br/>1. The Analog Interface 2. Binary-Hexadecimal-<br/>Decimal Equivalents 3. 7400 Series TTL<br/>4. Pinouts and Function Tables 5. SAP-1 Parts List<br/>6. 8085instructions 7. Memory Locations: Powers of 2<br/>8. Memory Locations: 16K and 8K Intervals<br/>9. Memory Locations: 4K Intervals 10. Memory<br/>Locations: 2K Intervals 11. Memory Locations: IK<br/>Intervals 12. Programming Models<br/>ContentsCHAPTER 6. ARITHMETIC-LOGIC UNITS<br/>PART 1<br/>Digital Principles 1<br/>CHAPTER 1. NUMBER SYSTEMS AND<br/>CODES 1<br/>1-1. Decimal Odometer 1-2. Binary Odometer<br/>1-3. Number Codes 1-4. Why Binary Numbers Are<br/>Used 1-5. Binary-to-Decimal Conversion<br/>1-6. Microprocessors 1-7. Decimal-to-Binary<br/>Conversion 1-8. Hexadecimal Numbers<br/>1-9. Hexadecimal-Binary Conversions<br/>1-10. Hexadecimal-to-Decimal Conversion<br/>1-11. Decimal-to-Hexadecimal Conversion<br/>1-12. BCD Numbers 1-13. The ASCII Code<br/>CHAPTER 2. GATES<br/>2-1. Inverters 2-2. or Gates<br/>2-4. Boolean Algebra<br/>2-3. AND Gates<br/>CHAPTER 3. MORE LOGIC GATES<br/>3-1. NOR Gates 3-2. De Morgan's First Theorem<br/>3-3. NAND Gates 3-4. De Morgan's Second Theorem<br/>3-5. EXCLUSIVE-OR Gates 3-6. The Controlled<br/>Inverter 3-7. exclusive-nor Gates<br/>CHAPTER 4. TTL CIRCUITS<br/>4-1. Digital Integrated Circuits 4-2. 7400 Devices<br/>4-3. TTL Characteristics 4-4. TTL Overview<br/>4-5. AND-OR-iNVERT Gates 4-6. Open-Collector Gates<br/>4-7. Multiplexers<br/>6-1. Binary Addition 6-2. Binary Subtraction<br/>6-3. Half Adders 6-4. Full Adders 6-5. Binary<br/>Adders 6-6. Signed Binary NOitibers 6-7. 2's<br/>Complement 6-8. 2's-CompIement Adder-Subtracter<br/>CHAPTER 7. FLIP-FLOPS<br/>7-1. Latches 7-2. Level Clocking 7-3. D Latches<br/>7-4. Edge-Triggered D Flip-Flops 7-5. Edge-Triggered<br/>JK Flip-Flops 7-6. JK Master-Slave Flip-Flop<br/>CHAPTER 8. REGISTERS AND<br/>COUNTERS<br/>8-1. Buffer Registers 8-2. Shift Registers<br/>8-3. Controlled Shift Registers 8-4. Ripple Counters<br/>8-5. Synchronous Counters 8-6. Ring Counters<br/>8-7. Other Counters 8-8. Three-State Registers<br/>8-9. Bus-Organized Computers<br/>9-3. RAMs<br/>Hexadecimal<br/>CHAPTER 9. MEMORIES<br/>9-1. ROMs 9-2. PROMs and EFROMs<br/>9-4. A Small TTL Memory 9-5.<br/>Addresses<br/>PART 2<br/>SAP (Simple-as-Possible)<br/>Computers<br/>CHAPTER 10. SAP-1<br/>10-1. Architecture -10-2. Instruction Set<br/>10-3. Programming SAP-1 10-4. Fetch Cycle<br/>10-5. Execution Cycle ip-6. The SAP-1<br/>Microprogram 10-7. The SAP-1 Schematic Diagram<br/>10-8. Microprogramming<br/>CHAPTER 5. BOOLEAN ALGEBRA AND<br/>KARNAUGH MAPS<br/>5-1. Boolean Relations 5-2. Sumtpf-Products Method<br/>5-3. Algebraic Simplification ^-4 Karnaugh Maps<br/>5-5. Pairs. Quads, and Octets 5i6. Karnaugh<br/>Simplifications 5-7. Don't-Care Conditions<br/>CHAPTER 11. SAP-2<br/>11-1. Bidirectional Registers 11-2. Architecture<br/>11-3. Memory-Reference Instructions 11-4. Register<br/>Instructions 11-5. Jump and Call Instructions<br/>11-6. Logic Instructions 11-7. Other Instructions<br/>11-8. SAP-2 Summary<br/>CHAPTER 12. SAP-3<br/>12-1. Programming Model 12-2. MOV and MVI<br/>12-3. Arithmetic Instructions 12-4. Increments,<br/>Decrements, and Rotates 12-5. Logic Instructions<br/>12-6. Arithmetic and Logic Immediates 12-7. Jump<br/>Instructions 12-8. Extended-Register Instructions<br/>12-9. Indirect Instructions 12-10. Stack Instructions<br/>CHAPTER 18. ARITHMETIC AND FLAGS<br/>New Concepts 18-1. Microprocessors and Numbers<br/>18-2. Arithmetic Instructions 18-3. Flag Instructions<br/>Specific Microprocessor Families 18.4 6502 Family<br/>18-5. 6800/6808 Family 18-6. 8080/8085/Z80 Family<br/>18-7. 8086/8088 Family<br/>P /\R ] 3<br/>Programming Popular<br/>Microprocessors<br/>CHAPTER 13. INTRODUCTION TO<br/>MICROPROCESSORS<br/>13-1. Computer Hardware<br/>13-2. Definition of a Microprocessor<br/>13-3. Some Common Uses for Microprocessors<br/>13-4. Microprocessors Featured in This Text<br/>13-5. Access to Microprocessors<br/>CHAPTER 14. PROGRAMMING AND<br/>LANGUAGES<br/>(4-1. Relationship between Electronics and Programming<br/>14-2. Programming 14-3. Fundamental Premise<br/>14-4. Flowcharts 14-5. Programming Languages<br/>14-6. Assembly Language 14-7. Worksheets<br/>CHAPTER 15. SYSTEM OVERVIEW<br/>New Concepts 15-1. Computer Architecture<br/>15-2. Microprocessor Architecture<br/>Specific Microprocessor Families<br/>15-3. 6502 Family 15-4. 6800/6808 Family<br/>15-5 . 8080/8085/Z80 Family 15-6. 8086/8088 Family<br/>CHAPTER 16. DATA TRANSFER<br/>INSTRUCTIONS<br/>New Concepts 16-1. CPU Control Instructions<br/>16-2. Data Transfer Instructions<br/>Specific Microprocessor Families<br/>16-3. 6502 Family 16-4. 6800/6808 Family<br/>16-5. 8080/8085/Z80 Family 16-6. 8086/8088 Family<br/>CHAPTER 17. ADDRESSING MODES—I<br/>What Is an Addressing Mode?<br/>17-2. The Paging Concept<br/>17-3. Basic Addressing Modes<br/>Specific Microprocessor Families 17-4. 6502 Family<br/>17-5 . 6800/6808 Family 17.6. 8080/8085/Z80 Family<br/>17.7. a086/8088 Family<br/>CHAPTER 19. LOGICAL INSTRUCTIONS<br/>New Concepts 19-1. The and Instruction<br/>19-2. The OR Instruction<br/>19-3. The EXCLUSIVE-OR (Egr. xor) Instruction<br/>19-4. The NOT Instruction<br/>19-5. The NEC (NEcate) Instruction<br/>Specific Microprocessor Families 19-6. 6502 Family<br/>19-7. 6800/6808 Family 19-8. 8080/8085/Z80 Family<br/>19-9. 8086/8088 Family<br/>CHAPTER 20. SHIFT AND ROTATE<br/>INSTRUCTIONS<br/>New Concepts 20-1. Rotating 20-2. Shifting<br/>20-3. An Example Specific Microprocessor Families<br/>20-4. 6502 Family 20-5. 6800/6808 Family<br/>20-6. 8080/8085/Z80 Family 20-7. 8086/8088 Family<br/>CHAPTER 21. ADDRESSING MODES—II<br/>New Concepts 21-1. Advanced Addressing Modes<br/>Specific Microprocessor Families 21-2. 6502 Family<br/>21-3. 6800/6808 Family 21-4. 8080/8085/Z80 Family<br/>21-5. 8086/8088 Family<br/>CHAPTER 22. branching AND LOOPS<br/>New Concepts 22-1. Unconditional Jumps<br/>22-2. Conditional Branching<br/>22-3. Compare and Test Instructions<br/>22-4. Increment and Decrement Instructions<br/>22-5. Nested Loops<br/>Specific Microprocessor Families 22-6. 6502 Family<br/>22-7. 6800/6808 Family 22-8. 8080/8085/Z80 Family<br/>22-9. 8086/8088 Family<br/>CHAPTER 23. SUBROUTINE AND STACK<br/>INSTRUCTIONS<br/>New Concepts 23-1. Stack and Stack Pointer<br/>23-2. Branching versus Subroutines<br/>23-3. How Do Subroutines Return?<br/>23-4. Pushing and Popping Registers<br/>Specific Microprocessor Families 23-5. 6502 Family<br/>23-6. 6800/6808 Family 23-7. 8080/8085/Z80 Family<br/>24-8. 8086/8088 Family<br/>PART 4<br/>Microprocessor Instruction<br/>Set Tables<br/>A.<br/>Expanded Table of 8085/8080 and Z80 (8080 Subset)<br/>Instructions Listed by Category 381<br/>Mini Table of 8085/8080 and Z80 (8080 Subset)<br/>Instructions Listed by Category 410<br/>Condensed Table of 8085/8080 and Z80 (8080)<br/>Instructions Listed by Category 415<br/>Condensed Table of 8085/8080 and Z80 (8080 Subset)<br/>Instructions Listed by Op Code 417<br/>Condensed Table of 8085/8080 and Z80 (8080 Subset)<br/>Instructions Listed Alphabetically by 8085/8080<br/>Mnemonic 419<br/>Condensed Table of 8085/8080 and Z80 (8080 Subset)<br/>Instructions Listed Alphabetically by Z80 Mnemonic<br/>421<br/>B.<br/>Expanded Table of 6800 Instructions Listed by Category<br/>422<br/>Short Table of 6800 Instructions Listed Alphabetically<br/>434<br/>Short Table of 6800 Instructions Listed by Category<br/>437<br/>Condensed Table of 6800 Instructions Listed by Category<br/>441<br/>Condensed Table of 6800 Instructions Listed<br/>Alphabetically 443<br/>Condensed Table of 6800 Instructions Listed by Op Code<br/>444<br/>Expanded Table of 8086/8088 Instructions Listed by<br/>Category 445<br/>Condensed Table of 8086/8088 Instructions Listed by<br/>Category 465<br/>Condensed Table of 8086/8088 Instructions Listed<br/>Alphabetically 469<br/>D.<br/>Expanded Table of 6502 Instructions Listed by Category<br/>471<br/>Short Table of 6502 Instructions Listed by Category<br/>478<br/>Condensed Table of 6502 Instructions Listed by Category<br/>480<br/>Condensed Table of 6502 Instructions Listed<br/>Alphabetically 481<br/>Condensed Table of 6502 Instructions Listed by Op Code<br/>482<br/>APPENDIXES<br/>1. The Analog Interface 2. Binary-Hexadecimal-<br/>Decimal Equivalents 3. 7400 Series TTL<br/>4. Pinouts and Function Tables 5. SAP-1 Parts List<br/>6. 8085instructions 7. Memory Locations: Powers of 2<br/>8. Memory Locations: 16K and 8K Intervals<br/>9. Memory Locations: 4K Intervals 10. Memory<br/>Locations: 2K Intervals 11. Memory Locations: IK<br/>Intervals 12. Programming Models<br/>Contents
650 ## - SUBJECT
Keyword	Computer
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type	General Books

Holdings
Withdrawn status	Lost status	Damaged status	Not for loan	Home library	Current library	Shelving location	Date acquired	Full call number	Accession number	Date last seen	Date last checked out	Koha item type
				Central Library, Sikkim University	Central Library, Sikkim University	General Book Section	31/05/2016	004 MAL/D	P18870	14/07/2018	14/07/2018	General Books